[llvm] r219927 - [mips] Marked the DI/EI instruction aliases as MIPS32r2
Vasileios Kalintiris
Vasileios.Kalintiris at imgtec.com
Thu Oct 16 08:23:53 PDT 2014
Author: vkalintiris
Date: Thu Oct 16 10:23:52 2014
New Revision: 219927
URL: http://llvm.org/viewvc/llvm-project?rev=219927&view=rev
Log:
[mips] Marked the DI/EI instruction aliases as MIPS32r2
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5751
Added:
llvm/trunk/test/MC/Mips/mips1/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips3/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips4/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips5/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips64/invalid-mips32r2.s
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips2/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips32/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Oct 16 10:23:52 2014
@@ -1489,8 +1489,8 @@ def : MipsInstAlias<"syscall", (SYSCALL
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
-def : MipsInstAlias<"ei", (EI ZERO), 1>;
-def : MipsInstAlias<"di", (DI ZERO), 1>;
+def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
+def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
Added: llvm/trunk/test/MC/Mips/mips1/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips32r2.s?rev=219927&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips32r2.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips32r2.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -13,7 +13,9 @@
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips3/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/invalid-mips32r2.s?rev=219927&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips3/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/invalid-mips32r2.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/invalid-mips32r2.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -8,7 +8,9 @@
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Thu Oct 16 10:23:52 2014
@@ -46,13 +46,15 @@
cvt.w.d $f20,$f14
cvt.w.s $f20,$f24
deret
- di $s8
+ di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
+ di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $zero,$25,$11
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
- ei $14
+ ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
+ ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret
floor.w.d $f14,$f11
floor.w.s $f8,$f9
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Thu Oct 16 10:23:52 2014
@@ -97,8 +97,12 @@
cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
+ di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
+ di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
+ ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
+ ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
Added: llvm/trunk/test/MC/Mips/mips4/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/invalid-mips32r2.s?rev=219927&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips4/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips5/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/invalid-mips32r2.s?rev=219927&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips5/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips64/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/invalid-mips32r2.s?rev=219927&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips64/invalid-mips32r2.s Thu Oct 16 10:23:52 2014
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Thu Oct 16 10:23:52 2014
@@ -62,7 +62,8 @@
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
deret
- di $s8
+ di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
+ di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$25,$11
@@ -109,7 +110,8 @@
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
- ei $14
+ ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
+ ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret
floor.l.d $f26,$f7
floor.l.s $f12,$f5
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=219927&r1=219926&r2=219927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Thu Oct 16 10:23:52 2014
@@ -104,10 +104,14 @@
dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
+ di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
+ di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
+ ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
+ ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
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