[PATCH] [ARM] Do not select SMULW[BT] or SMLAW[BT]

[Oliver Stannard]

The current instruction selection patterns for SMULW[BT] and SMLAW[BT]
are incorrect. These instructions multiply a 32-bit and a 16-bit value
(both signed) and return the top 32 bits of the 48-bit result. This
preserves the 16 bits of overflow, whereas the patterns they currently
match truncate the result to 16 bits then sign extend.

To select these instructions, we would need to match an ISD::SMUL_LOHI,
a sign extend, two shifts and an or. There is no way to match SMUL_LOHI
in an instruction pattern as it defines multiple values (please correct
me if I am wrong), so this would have to be done in C++. Since this
pattern is not likely to occur often, I will raise a bugzilla ticket for
it.

This fixes http://llvm.org/bugs/show_bug.cgi?id=19396

http://reviews.llvm.org/D5824

Files:
  lib/Target/ARM/ARMInstrInfo.td
  lib/Target/ARM/ARMInstrThumb2.td
  test/CodeGen/ARM/smulw.ll
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