[PATCH] [mips] Add support for COP1's Branch-On-Cond-Likely instructions

[Daniel Sanders]

LGTM with hasDelaySlot changed to 0 for the branch likelies and a test that ensures that the assembler doesn't insert nop's after branch likelies

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Comment at: lib/Target/Mips/MipsInstrFPU.td:565
@@ -564,1 +564,3 @@
            BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F>,
+            BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
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BC1F_FT is almost right but hasDelaySlot needs to be 0 for branch likelies.

http://reviews.llvm.org/D5802