[llvm] r219826 - Enable the instruction printer in HexagonMCTargetDesc
Sid Manning
sidneym at codeaurora.org
Wed Oct 15 11:27:40 PDT 2014
Author: sidneym
Date: Wed Oct 15 13:27:40 2014
New Revision: 219826
URL: http://llvm.org/viewvc/llvm-project?rev=219826&view=rev
Log:
Enable the instruction printer in HexagonMCTargetDesc
This adds the MCInstPrinter to the LLVMHexagonDesc library and removes
the dependency LLVMHexagonAsmPrinter had on LLVMHexagonDesc. This is
a prerequisite needed by the disassembler.
Phabricator Revision: http://reviews.llvm.org/D5734
Modified:
llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt
Modified: llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp?rev=219826&r1=219825&r2=219826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp Wed Oct 15 13:27:40 2014
@@ -29,6 +29,43 @@ using namespace llvm;
#include "HexagonGenAsmWriter.inc"
const char HexagonInstPrinter::PacketPadding = '\t';
+// Return the minimum value that a constant extendable operand can have
+// without being extended.
+static int getMinValue(uint64_t TSFlags) {
+ unsigned isSigned =
+ (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
+ unsigned bits =
+ (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
+
+ if (isSigned)
+ return -1U << (bits - 1);
+ else
+ return 0;
+}
+
+// Return the maximum value that a constant extendable operand can have
+// without being extended.
+static int getMaxValue(uint64_t TSFlags) {
+ unsigned isSigned =
+ (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
+ unsigned bits =
+ (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
+
+ if (isSigned)
+ return ~(-1U << (bits - 1));
+ else
+ return ~(-1U << bits);
+}
+
+// Return true if the instruction must be extended.
+static bool isExtended(uint64_t TSFlags) {
+ return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
+}
+
+// Return true if the instruction may be extended based on the operand value.
+static bool isExtendable(uint64_t TSFlags) {
+ return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
+}
StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
@@ -116,9 +153,20 @@ void HexagonInstPrinter::printImmOperand
void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) const {
- const HexagonMCInst *HMCI = static_cast<const HexagonMCInst*>(MI);
- if (HMCI->isConstExtended())
+ const MCOperand &MO = MI->getOperand(OpNo);
+ const MCInstrDesc &MII = getMII().get(MI->getOpcode());
+
+ assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
+ "Expecting an extendable operand");
+
+ if (MO.isExpr() || isExtended(MII.TSFlags)) {
O << "#";
+ } else if (MO.isImm()) {
+ int ImmValue = MO.getImm();
+ if (ImmValue < getMinValue(MII.TSFlags) ||
+ ImmValue > getMaxValue(MII.TSFlags))
+ O << "#";
+ }
printOperand(MI, OpNo, O);
}
Modified: llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt?rev=219826&r1=219825&r2=219826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt Wed Oct 15 13:27:40 2014
@@ -19,5 +19,5 @@
type = Library
name = HexagonAsmPrinter
parent = Hexagon
-required_libraries = HexagonDesc MC Support
+required_libraries = MC Support
add_to_library_groups = Hexagon
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=219826&r1=219825&r2=219826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Wed Oct 15 13:27:40 2014
@@ -74,6 +74,14 @@ static MCCodeGenInfo *createHexagonMCCod
X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
return X;
}
+static MCInstPrinter *createHexagonMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ const MCInstrInfo &MII,
+ const MCRegisterInfo &MRI,
+ const MCSubtargetInfo &STI) {
+ return new HexagonInstPrinter(MAI, MII, MRI);
+}
// Force static initialization.
extern "C" void LLVMInitializeHexagonTargetMC() {
@@ -99,4 +107,8 @@ extern "C" void LLVMInitializeHexagonTar
// Register the MC Code Emitter
TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
createHexagonMCCodeEmitter);
+
+ // Register the MC Inst Printer
+ TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
+ createHexagonMCInstPrinter);
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt?rev=219826&r1=219825&r2=219826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt Wed Oct 15 13:27:40 2014
@@ -19,5 +19,5 @@
type = Library
name = HexagonDesc
parent = Hexagon
-required_libraries = HexagonInfo MC Support
+required_libraries = HexagonAsmPrinter HexagonInfo MC Support
add_to_library_groups = Hexagon
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