[PATCH] [ARM] [CodeGen] Do not emit intermediate register for zero FP immediate

[Renato Golin]

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:3246
@@ +3245,3 @@
+    // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
+    // created by LowerConstantFP().
+    SDValue BitcastOp = Op->getOperand(0);
----------------
I'd say this is a bit too specific on what LowerConstantFP does today, which may change. Wouldn't any fp bitcast work in this case, if the value being casted is zero?

http://reviews.llvm.org/D5456