[PATCH v2 3/3] DAGCombiner: Add (A - (0-B)) -> A+B optimization

[Jan Vesely]

Hi,

I switched ADDC and SUBB to sue sign_extend_inreg instead of sub 0, x.
so this patch is no longer needed.
I plan to drop it entirely, but I can resubmit with a dedicated test if
you think it's useful.

thanks,
jan

On Wed, 2014-09-24 at 20:27 -0400, Jan Vesely wrote:
> v2: tighten r600 add64 tests that use this optimization
> 
> CC: Chad Rosier <mcrosier at codeaurora.org>
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
>  lib/CodeGen/SelectionDAG/DAGCombiner.cpp |  4 ++++
>  test/CodeGen/R600/add.ll                 | 18 +++++++++++++++---
>  2 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> index 33e7059..bc39fe3 100644
> --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> @@ -1794,6 +1794,10 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
>    // fold (A+B)-B -> A
>    if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
>      return N0.getOperand(0);
> +  // fold (A - (0-B)) -> A+B
> +  if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
> +      cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
> +    return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1.getOperand(1));
>    // fold C2-(A+C1) -> (C2-C1)-A
>    if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
>      SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
> diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll
> index fddb951..8584f49 100644
> --- a/test/CodeGen/R600/add.ll
> +++ b/test/CodeGen/R600/add.ll
> @@ -120,9 +120,13 @@ entry:
>  ; SI: S_ADD_U32
>  ; SI: S_ADDC_U32
>  
> -; EG-DAG: ADD_INT
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> +; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
>  ; EG-DAG: ADDC_UINT
>  ; EG-DAG: ADD_INT
> +; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> +; EG-NOT: SUB
>  define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
>  entry:
>    %0 = add i64 %a, %b
> @@ -138,9 +142,13 @@ entry:
>  ; FUNC-LABEL: @add64_sgpr_vgpr
>  ; SI-NOT: V_ADDC_U32_e32 s
>  
> -; EG-DAG: ADD_INT
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> +; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
>  ; EG-DAG: ADDC_UINT
>  ; EG-DAG: ADD_INT
> +; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> +; EG-NOT: SUB
>  define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
>  entry:
>    %0 = load i64 addrspace(1)* %in
> @@ -154,9 +162,13 @@ entry:
>  ; SI: S_ADD_U32
>  ; SI: S_ADDC_U32
>  
> -; EG-DAG: ADD_INT
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> +; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
>  ; EG-DAG: ADDC_UINT
>  ; EG-DAG: ADD_INT
> +; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> +; EG-NOT: SUB
>  define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
>  entry:
>    %0 = icmp eq i64 %a, 0

-- 
Jan Vesely <jan.vesely at rutgers.edu>
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