[PATCH 1/1] SelectionDAG: Add sext_inreg optimizations

[Matt Arsenault]

On Oct 13, 2014, at 2:28 PM, Jan Vesely <jan.vesely at rutgers.edu> wrote:

> On Mon, 2014-10-13 at 10:11 -0700, Matt Arsenault wrote:
>> On Oct 13, 2014, at 10:00 AM, Jan Vesely <jan.vesely at rutgers.edu> wrote:
>> 
>>> On Mon, 2014-10-13 at 09:46 -0700, Matt Arsenault wrote:
>>>> On Oct 13, 2014, at 9:14 AM, Jan Vesely <jan.vesely at rutgers.edu> wrote:
>>>> 
>>>>> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
>>>>> ---
>>>>> 
>>>>> lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 22 ++++++++++++++++++++++
>>>>> test/CodeGen/R600/sext-eliminate.ll      | 26 ++++++++++++++++++++++++++
>>>>> 2 files changed, 48 insertions(+)
>>>>> create mode 100644 test/CodeGen/R600/sext-eliminate.ll
>>>>> 
>>>>> diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>> index 76442fb..fdffd77 100644
>>>>> --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>> +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>> @@ -1680,6 +1680,17 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
>>>>>   return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
>>>>> }
>>>>> 
>>>>> +  // add X, (sextinreg i1) -> sub X, (and i1 1)
>>> 
>>> I changed the comments to
>>> // add X, (sextinreg Y i1) -> sub X, (and Y 1)
>>> 
>>>>> +  if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
>>>>> +    VTSDNode *TN = static_cast<VTSDNode*>(N1.getOperand(1).getNode());
>>>> 
>>>> Also I don’t think you need the .getNode() here
>>> 
>>> using
>>> static_cast<VTSDNode*>(N1.getOperand(1))
>>> produces invalid static_cast error.
>>> I think overloaded operator -> only enables to run methods of the
>>> latter, is that what you had in mind?
>> 
>> I didn’t even notice the static_ part there. You can use regular LLVM
>> cast<> for different SDNode types
> 
> thanks. now it works even without getNode().
> I switched to dyn_cast for added paranoia.
> v2 incoming

You should use cast<>. There’s a bug somewhere else producing an invalid sext_in_reg if that operand isn’t a VTSDNode 

> 
>> 
>>> 
>>> 
>>> jan
>>> 
>>>> 
>>>>> +    if (TN->getVT() == MVT::i1) {
>>>>> +      SDLoc DL(N);
>>>>> +      SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
>>>>> +                                 DAG.getConstant(1, VT));
>>>>> +      return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
>>>>> +    }
>>>>> +  }
>>>>> +
>>>>> return SDValue();
>>>>> }
>>>>> 
>>>>> @@ -1845,6 +1856,17 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
>>>>>                                VT);
>>>>>   }
>>>>> 
>>>>> +  // sub X, (sextinreg i1) -> add X, (and i1 1)
>>>>> +  if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
>>>>> +    VTSDNode *TN = static_cast<VTSDNode*>(N1.getOperand(1).getNode());
>>>>> +    if (TN->getVT() == MVT::i1) {
>>>>> +      SDLoc DL(N);
>>>>> +      SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
>>>>> +                                 DAG.getConstant(1, VT));
>>>>> +      return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
>>>>> +    }
>>>>> +  }
>>>>> +
>>>>> return SDValue();
>>>>> }
>>>>> 
>>>>> diff --git a/test/CodeGen/R600/sext-eliminate.ll b/test/CodeGen/R600/sext-eliminate.ll
>>>>> new file mode 100644
>>>>> index 0000000..0c17a7a
>>>>> --- /dev/null
>>>>> +++ b/test/CodeGen/R600/sext-eliminate.ll
>>>>> @@ -0,0 +1,26 @@
>>>>> +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
>>>>> +
>>>>> +
>>>>> +; FUNC-LABEL: {{^}}sext_in_reg_i1_i32_add:
>>>>> +
>>>>> +; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
>>>>> +; EG: SUB_INT {{[* ]*}}[[RES]]
>>>>> +; EG-NOT: BFE
>>>>> +define void @sext_in_reg_i1_i32_add(i32 addrspace(1)* %out, i1 %a, i32 %b) {
>>>>> +  %sext = sext i1 %a to i32
>>>>> +  %res = add i32 %b, %sext 
>>>>> +  store i32 %res, i32 addrspace(1)* %out
>>>>> +  ret void
>>>>> +}
>>>>> +
>>>>> +; FUNC-LABEL: {{^}}sext_in_reg_i1_i32_sub:
>>>>> +
>>>>> +; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
>>>>> +; EG: ADD_INT {{[* ]*}}[[RES]]
>>>>> +; EG-NOT: BFE
>>>>> +define void @sext_in_reg_i1_i32_sub(i32 addrspace(1)* %out, i1 %a, i32 %b) {
>>>>> +  %sext = sext i1 %a to i32
>>>>> +  %res = sub i32 %b, %sext 
>>>>> +  store i32 %res, i32 addrspace(1)* %out
>>>>> +  ret void
>>>>> +}
>>>>> -- 
>>>>> 1.9.3
>>>>> 
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>> 
>>> 
>>> -- 
>>> Jan Vesely <jan.vesely at rutgers.edu>
>> 
> 
> -- 
> Jan Vesely <jan.vesely at rutgers.edu>