[llvm] r219518 - implement integer compare in mips fast-isel
Reed Kotler
rkotler at mips.com
Fri Oct 10 10:39:52 PDT 2014
Author: rkotler
Date: Fri Oct 10 12:39:51 2014
New Revision: 219518
URL: http://llvm.org/viewvc/llvm-project?rev=219518&view=rev
Log:
implement integer compare in mips fast-isel
Summary: implement SelectCmp (integer compare ) in mips fast-isel
Test Plan:
icmpa.ll
also ran 4 test-suite flavors mips32 r1/r2 O0/O2
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits, rfuhler, mcrosier
Differential Revision: http://reviews.llvm.org/D5566
Added:
llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=219518&r1=219517&r2=219518&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Fri Oct 10 12:39:51 2014
@@ -85,10 +85,13 @@ private:
bool SelectFPExt(const Instruction *I);
bool SelectFPTrunc(const Instruction *I);
bool SelectFPToI(const Instruction *I, bool IsSigned);
+ bool SelectCmp(const Instruction *I);
bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT);
+ unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
+
unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
unsigned MaterializeInt(const Constant *C, MVT VT);
@@ -171,6 +174,21 @@ bool MipsFastISel::ComputeAddress(const
return Addr.Base.Reg != 0;
}
+unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
+ bool IsUnsigned) {
+ unsigned VReg = getRegForValue(V);
+ if (VReg == 0)
+ return 0;
+ MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
+ if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ if (!EmitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
+ return 0;
+ VReg = TempReg;
+ }
+ return VReg;
+}
+
bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment) {
//
@@ -543,6 +561,84 @@ bool MipsFastISel::SelectFPToI(const Ins
return true;
}
+//
+// Because of how SelectCmp is called with fast-isel, you can
+// end up with redundant "andi" instructions after the sequences emitted below.
+// We should try and solve this issue in the future.
+//
+bool MipsFastISel::SelectCmp(const Instruction *I) {
+ const CmpInst *CI = cast<CmpInst>(I);
+ bool IsUnsigned = CI->isUnsigned();
+ const Value *Left = I->getOperand(0), *Right = I->getOperand(1);
+
+ unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
+ if (LeftReg == 0)
+ return false;
+ unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
+ if (RightReg == 0)
+ return false;
+ unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+
+ switch (CI->getPredicate()) {
+ default:
+ return false;
+ case CmpInst::ICMP_EQ: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+ EmitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
+ break;
+ }
+ case CmpInst::ICMP_NE: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+ EmitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
+ break;
+ }
+ case CmpInst::ICMP_UGT: {
+ EmitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
+ break;
+ }
+ case CmpInst::ICMP_ULT: {
+ EmitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
+ break;
+ }
+ case CmpInst::ICMP_UGE: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
+ EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ break;
+ }
+ case CmpInst::ICMP_ULE: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
+ EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ break;
+ }
+ case CmpInst::ICMP_SGT: {
+ EmitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
+ break;
+ }
+ case CmpInst::ICMP_SLT: {
+ EmitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
+ break;
+ }
+ case CmpInst::ICMP_SGE: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
+ EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ break;
+ }
+ case CmpInst::ICMP_SLE: {
+ unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+ EmitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
+ EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ break;
+ }
+ }
+ updateValueMap(I, ResultReg);
+ return true;
+}
+
bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
if (!TargetSupported)
return false;
@@ -568,6 +664,9 @@ bool MipsFastISel::fastSelectInstruction
return SelectFPToI(I, /*isSigned*/ true);
case Instruction::FPToUI:
return SelectFPToI(I, /*isSigned*/ false);
+ case Instruction::ICmp:
+ case Instruction::FCmp:
+ return SelectCmp(I);
}
return false;
}
Added: llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll?rev=219518&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll Fri Oct 10 12:39:51 2014
@@ -0,0 +1,203 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+ at c = global i32 4, align 4
+ at d = global i32 9, align 4
+ at uc = global i32 4, align 4
+ at ud = global i32 9, align 4
+ at b1 = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @eq() {
+entry:
+; CHECK-LABEL: .ent eq
+
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp eq i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ne() {
+entry:
+; CHECK-LABEL: .ent ne
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp ne i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ugt() {
+entry:
+; CHECK-LABEL: .ent ugt
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ugt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ult() {
+entry:
+; CHECK-LABEL: .ent ult
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ult i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @uge() {
+entry:
+; CHECK-LABEL: .ent uge
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp uge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ule() {
+entry:
+; CHECK-LABEL: .ent ule
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ule i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sgt() {
+entry:
+; CHECK-LABEL: .ent sgt
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sgt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @slt() {
+entry:
+; CHECK-LABEL: .ent slt
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp slt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sge() {
+entry:
+; CHECK-LABEL: .ent sge
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sle() {
+entry:
+; CHECK-LABEL: .ent sle
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sle i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+
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