[llvm] r219428 - R600/SI: Legalize CopyToReg during instruction selection

[Tom Stellard]

Author: tstellar
Date: Thu Oct  9 14:06:00 2014
New Revision: 219428

URL: http://llvm.org/viewvc/llvm-project?rev=219428&view=rev
Log:
R600/SI: Legalize CopyToReg during instruction selection

The instruction emitter will crash if it encounters a CopyToReg
node with a non-register operand like FrameIndex.

Added:
    llvm/trunk/test/CodeGen/R600/copy-to-reg.ll
Modified:
    llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
    llvm/trunk/lib/Target/R600/SIISelLowering.cpp
    llvm/trunk/lib/Target/R600/SIISelLowering.h

Modified: llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp?rev=219428&r1=219427&r2=219428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp Thu Oct  9 14:06:00 2014
@@ -487,9 +487,16 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNod
   case AMDGPUISD::DIV_SCALE: {
     return SelectDIV_SCALE(N);
   }
+  case ISD::CopyToReg: {
+    const SITargetLowering& Lowering =
+      *static_cast<const SITargetLowering*>(getTargetLowering());
+    Lowering.legalizeTargetIndependentNode(N, *CurDAG);
+    break;
+  }
   case ISD::ADDRSPACECAST:
     return SelectAddrSpaceCast(N);
   }
+
   return SelectCode(N);
 }
 

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=219428&r1=219427&r2=219428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Thu Oct  9 14:06:00 2014
@@ -1920,28 +1920,26 @@ void SITargetLowering::adjustWritemask(M
   }
 }
 
-/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
-/// LLVM assumes that all INSERT_SUBREG inputs are registers.
-static void legalizeInsertSubreg(MachineSDNode *InsertSubreg,
-                                 SelectionDAG &DAG) {
-
-  assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
+/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
+/// with frame index operands.
+/// LLVM assumes that inputs are to these instructions are registers.
+void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
+                                                     SelectionDAG &DAG) const {
 
   SmallVector<SDValue, 8> Ops;
-  for (unsigned i = 0; i < 2; ++i) {
-    if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
-      Ops.push_back(InsertSubreg->getOperand(i));
+  for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
+    if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
+      Ops.push_back(Node->getOperand(i));
       continue;
     }
 
-    SDLoc DL(InsertSubreg);
+    SDLoc DL(Node);
     Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
-                                     InsertSubreg->getOperand(i).getValueType(),
-                                     InsertSubreg->getOperand(i)), 0));
+                                     Node->getOperand(i).getValueType(),
+                                     Node->getOperand(i)), 0));
   }
 
-  DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
-                         InsertSubreg->getOperand(2));
+  DAG.UpdateNodeOperands(Node, Ops);
 }
 
 /// \brief Fold the instructions after selecting them.

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.h?rev=219428&r1=219427&r2=219428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.h (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.h Thu Oct  9 14:06:00 2014
@@ -101,6 +101,7 @@ public:
   int32_t analyzeImmediate(const SDNode *N) const;
   SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
                                unsigned Reg, EVT VT) const override;
+  void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
 };
 
 } // End namespace llvm

Added: llvm/trunk/test/CodeGen/R600/copy-to-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/copy-to-reg.ll?rev=219428&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/copy-to-reg.ll (added)
+++ llvm/trunk/test/CodeGen/R600/copy-to-reg.ll Thu Oct  9 14:06:00 2014
@@ -0,0 +1,26 @@
+; RUN: llc -march=r600 -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
+
+; Test that CopyToReg instructions don't have non-register operands prior
+; to being emitted.
+
+; Make sure this doesn't crash
+; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
+define void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+entry:
+  %alloca = alloca [16 x i32]
+  br label %loop
+
+loop:
+  %inc = phi i32 [0, %entry], [%inc.i, %loop]
+  %ptr = getelementptr [16 x i32]* %alloca, i32 0, i32 %inc
+  store i32 %inc, i32* %ptr
+  %inc.i = add i32 %inc, 1
+  %cnd = icmp uge i32 %inc.i, 16
+  br i1 %cnd, label %done, label %loop
+
+done:
+  %tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 0
+  %tmp1 = load i32* %tmp0
+  store i32 %tmp1, i32 addrspace(1)* %out
+  ret void
+}