[llvm] r219420 - R600/SI: Legalize INSERT_SUBREG instructions during PostISelFolding

[Tom Stellard]

Author: tstellar
Date: Thu Oct  9 13:09:15 2014
New Revision: 219420

URL: http://llvm.org/viewvc/llvm-project?rev=219420&view=rev
Log:
R600/SI: Legalize INSERT_SUBREG instructions during PostISelFolding

LLVM assumes INSERT_SUBREG will always have register operands, so
we need to legalize non-register operands, like FrameIndexes, to
avoid random assertion failures.

Added:
    llvm/trunk/test/CodeGen/R600/insert_subreg.ll
Modified:
    llvm/trunk/lib/Target/R600/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=219420&r1=219419&r2=219420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Thu Oct  9 13:09:15 2014
@@ -1920,6 +1920,30 @@ void SITargetLowering::adjustWritemask(M
   }
 }
 
+/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
+/// LLVM assumes that all INSERT_SUBREG inputs are registers.
+static void legalizeInsertSubreg(MachineSDNode *InsertSubreg,
+                                 SelectionDAG &DAG) {
+
+  assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
+
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0; i < 2; ++i) {
+    if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
+      Ops.push_back(InsertSubreg->getOperand(i));
+      continue;
+    }
+
+    SDLoc DL(InsertSubreg);
+    Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
+                                     InsertSubreg->getOperand(i).getValueType(),
+                                     InsertSubreg->getOperand(i)), 0));
+  }
+
+  DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
+                         InsertSubreg->getOperand(2));
+}
+
 /// \brief Fold the instructions after selecting them.
 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
                                           SelectionDAG &DAG) const {
@@ -1930,6 +1954,11 @@ SDNode *SITargetLowering::PostISelFoldin
   if (TII->isMIMG(Node->getMachineOpcode()))
     adjustWritemask(Node, DAG);
 
+  if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG) {
+    legalizeTargetIndependentNode(Node, DAG);
+    return Node;
+  }
+
   return legalizeOperands(Node, DAG);
 }
 

Added: llvm/trunk/test/CodeGen/R600/insert_subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/insert_subreg.ll?rev=219420&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/insert_subreg.ll (added)
+++ llvm/trunk/test/CodeGen/R600/insert_subreg.ll Thu Oct  9 13:09:15 2014
@@ -0,0 +1,15 @@
+; RUN: llc -march=r600 -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
+
+; Test that INSERT_SUBREG instructions don't have non-register operands after
+; instruction selection.
+
+; Make sure this doesn't crash
+; CHECK-LABEL: test:
+define void @test(i64 addrspace(1)* %out) {
+entry:
+  %tmp0 = alloca [16 x i32]
+  %tmp1 = ptrtoint [16 x i32]* %tmp0 to i32
+  %tmp2 = sext i32 %tmp1 to i64
+  store i64 %tmp2, i64 addrspace(1)* %out
+  ret void
+}