[PATCH] [PATCH] Test case and FastISel fixes with FeatureVSX enabled

[Bill Seurer]

On 10/8/2014 6:09 PM, Eric Christopher wrote:
> There's more seemingly of these as well, but calling out each one
> separately seems to be a bit verbose.
>
> Thoughts?

This work started as getting the test cases to work that failed with 
FeatureVSX turned on.  There turned out to be 3 things that were causing 
problems when VSX is turned on:
1) FastISel not being able to handle VSX registers and hitting assertion 
checks.
2) Different (i.e., VSX) operations being generated in some test cases 
than were being checked for.  For these I changed the exiting test to 
use -mattr=-vsx and then added new checks for -mattr=+vsx.  The new 
checks in some cases are substantially the same because the same code is 
generated for parts of the test cases with or without VSX activated.
3) Basic incompatibility between options in some test cases; 32 bit 
compilations or targeting Darwin + VSX doesn't work.  For the tests that 
failed (and just the ones that failed) I just added -mattr=-vsx.  I 
thought about changing all the tests that had "bad" combinations but 
there were more than a hundred so I left that for later (maybe).

#2 and #3 are what all the test case changes are about and need to be 
done irregardless of the FastISel changes.  Back a long ways in the 
conversation I asked about doing the test case changes separately but no 
one responded then.

The Generic select-cc.ll test fails with VSX turned on.  Note that there 
is an identical test in CodeGen/PowerPC which also fails though that one 
uses the option -march=ppc32.

FAIL: LLVM :: CodeGen/Generic/select-cc.ll (9642 of 19384)
******************** TEST 'LLVM :: CodeGen/Generic/select-cc.ll' FAILED
. . .
LLVM ERROR: Cannot select: 0x1001e5b99f0: v2f64 = select_cc 
0x1001e5b96d8, 0x1001e5b97e0, 0x1001e5b7158, 0x1001e5b6f48,
0x1001e5b98e8 [ORD=4] [ID=20]
   0x1001e5b96d8: i1 = and 0x1001e5b7788, 0x1001e5b95d0 [ORD=4] [ID=19]
     0x1001e5b7788: i1 = setcc 0x1001e5b7470, 0x1001e5b9af8, 
0x1001e5b7260 [ORD=4] [ID=17]
       0x1001e5b7470: f64 = extract_vector_elt 0x1001e5b6f48, 
0x1001e5b7368 [ORD=2] [ID=15]
         0x1001e5b6f48: v2f64,ch = CopyFromReg 0x1001e582790, 
0x1001e5b6e40 [ORD=1] [ID=12]
           0x1001e5b6e40: v2f64 = Register %vreg0 [ID=1]
         0x1001e5b7368: i64 = Constant<0> [ID=3]
       0x1001e5b9af8: f64,ch = load 0x1001e582790, 0x1001e5b9d08, 
0x1001e5b7cb0<LD4[ConstantPool], anyext from f32> [ID=1
6]
         0x1001e5b9d08: i64 = PPCISD::TOC_ENTRY 0x1001e5b7578, 
0x1001e5b9c00 [ID=14]
           0x1001e5b7578: i64 = TargetConstantPool<float 0.000000e+00> 0 
[ID=10]
           0x1001e5b9c00: i64 = Register %X2 [ID=11]
         0x1001e5b7cb0: i64 = undef [ID=9]
     0x1001e5b95d0: i1 = setcc 0x1001e5b7470, 0x1001e5b9af8, 
0x1001e5b7890 [ORD=4] [ID=18]
       0x1001e5b7470: f64 = extract_vector_elt 0x1001e5b6f48, 
0x1001e5b7368 [ORD=2] [ID=15]
         0x1001e5b6f48: v2f64,ch = CopyFromReg 0x1001e582790, 
0x1001e5b6e40 [ORD=1] [ID=12]
           0x1001e5b6e40: v2f64 = Register %vreg0 [ID=1]
         0x1001e5b7368: i64 = Constant<0> [ID=3]
       0x1001e5b9af8: f64,ch = load 0x1001e582790, 0x1001e5b9d08, 
0x1001e5b7cb0<LD4[ConstantPool], anyext from f32> [ID=1
6]
         0x1001e5b9d08: i64 = PPCISD::TOC_ENTRY 0x1001e5b7578, 
0x1001e5b9c00 [ID=14]
           0x1001e5b7578: i64 = TargetConstantPool<float 0.000000e+00> 0 
[ID=10]
           0x1001e5b9c00: i64 = Register %X2 [ID=11]
         0x1001e5b7cb0: i64 = undef [ID=9]
   0x1001e5b97e0: i1 = Constant<0> [ID=7]
   0x1001e5b7158: v2f64,ch = CopyFromReg 0x1001e582790, 0x1001e5b7050 
[ORD=1] [ID=13]
     0x1001e5b7050: v2f64 = Register %vreg1 [ID=2]
   0x1001e5b6f48: v2f64,ch = CopyFromReg 0x1001e582790, 0x1001e5b6e40 
[ORD=1] [ID=12]
     0x1001e5b6e40: v2f64 = Register %vreg0 [ID=1]
In function: vector_select
-- 

-Bill Seurer