[PATCH] R600/SI: Set isAllocatable = 0 on special register classes.

[Tom Stellard]

On Thu, Oct 09, 2014 at 12:02:37AM +0000, Matt Arsenault wrote:
> I'm not sure if this fixes any real problems.
> copyPhysReg already has a comment that SCC should never be copied,
> so set CopyCost = -1.
>     

I don't think setting isAllocatable = 0; will work for any of these classes,
because there are instructions defined to use virtual registers from these
classes which need to have them be allocated.

-Tom
> These all seem obviously not allocatable, but I'm not sure about VCC
> since most instructions that use it can also use an arbitrary SGPR
> pair instead.
> 
> http://reviews.llvm.org/D5686
> 
> Files:
>   lib/Target/R600/SIRegisterInfo.td

> Index: lib/Target/R600/SIRegisterInfo.td
> ===================================================================
> --- lib/Target/R600/SIRegisterInfo.td
> +++ lib/Target/R600/SIRegisterInfo.td
> @@ -170,11 +170,23 @@
>  //===----------------------------------------------------------------------===//
>  
>  // Special register classes for predicates and the M0 register
> -def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
> +def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
> +  let CopyCost = -1;
> +  let isAllocatable = 0;
> +}
> +
> +// XXX - Should this be isAllocatable = 0?
>  def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
> -def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
> +
> +def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)> {
> +  let isAllocatable = 0;
> +}
> +
> +// XXX - Seems like this should be isAllocatable = 0, but that seems
> +// to break tests.
>  def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
>  
> +
>  // Register class for all scalar registers (SGPRs + Special Registers)
>  def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
>    (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)

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