[PATCH] ARM64 - Conditional branch peephole

[Gerolf Hoflehner]

Hi t.p.northover,

Converts CSINC-branch sequence to single conditional branch

On ARM64 the optimization generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the CINCR and the original branch.

Examples:
1.
   csinc  w9, wzr, wzr, <condition code>
   tbnz   w9, #0, 0x44
 to
   b.<inverted condition code>

 2.
   csinc w9, wzr, wzr, <condition code>
   tbz   w9, #0, 0x44
 to
   b.<condition code>

http://reviews.llvm.org/D5637

Files:
  include/llvm/Target/TargetInstrInfo.h
  lib/CodeGen/PeepholeOptimizer.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.h
  test/CodeGen/AArch64/arm64-bcc.ll
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