[llvm] r218986 - Adding skeleton for unit testing Hexagon Code Emission
Chad Rosier
mcrosier at codeaurora.org
Fri Oct 3 06:45:39 PDT 2014
> Author: sidneym
> Date: Fri Oct 3 08:18:11 2014
> New Revision: 218986
>
> URL: http://llvm.org/viewvc/llvm-project?rev=218986&view=rev
> Log:
> Adding skeleton for unit testing Hexagon Code Emission
>
> Adding and modifying CMakeLists.txt files to run unit tests under
> unittests/Target/* if the directory exists. Adding basic unit test to
> check
> that code emitter object can be retrieved.
>
> Differential Revision: http://reviews.llvm.org/D5523
> Change by: Colin LeMahieu
>
> Added:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
> Modified:
> llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> llvm/trunk/unittests/MC/CMakeLists.txt
>
> Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=218986&r1=218985&r2=218986&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Fri Oct 3 08:18:11 2014
> @@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS Hexagon.td)
>
> tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
> tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
> +tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
> tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
> tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt?rev=218986&r1=218985&r2=218986&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt Fri Oct 3
> 08:18:11 2014
> @@ -1,5 +1,8 @@
> add_llvm_library(LLVMHexagonDesc
> HexagonMCAsmInfo.cpp
> + HexagonMCCodeEmitter.cpp
> HexagonMCInst.cpp
> HexagonMCTargetDesc.cpp
> )
> +
> +add_dependencies(LLVMHexagonDesc HexagonCommonTableGen)
> \ No newline at end of file
Please add a newline to the end of the CMakeLists.txt.
>
> Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=218986&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> (added)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> Fri Oct 3 08:18:11 2014
> @@ -0,0 +1,88 @@
> +//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions
> ------------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "Hexagon.h"
> +#include "MCTargetDesc/HexagonBaseInfo.h"
> +#include "MCTargetDesc/HexagonMCCodeEmitter.h"
> +#include "MCTargetDesc/HexagonMCTargetDesc.h"
> +#include "MCTargetDesc/HexagonMCInst.h"
> +#include "llvm/ADT/Statistic.h"
> +#include "llvm/MC/MCCodeEmitter.h"
> +#include "llvm/MC/MCContext.h"
> +#include "llvm/MC/MCExpr.h"
> +#include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCInstrInfo.h"
> +#include "llvm/MC/MCRegisterInfo.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/raw_ostream.h"
> +
> +#define DEBUG_TYPE "mccodeemitter"
> +
> +using namespace llvm;
> +using namespace Hexagon;
> +
> +STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
> +
> +namespace {
> +/// \brief 10.6 Instruction Packets
> +/// \brief Possible values for instruction packet parse field.
> +enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3
> };
> +/// \brief Returns the packet bits based on instruction position.
> +uint32_t getPacketBits(HexagonMCInst const &HMI) {
> + unsigned const ParseFieldOffset = 14;
> + ParseField Field = HMI.isPacketEnd() ? ParseField::end :
> ParseField::last0;
> + return static_cast <uint32_t> (Field) << ParseFieldOffset;
> +}
> +void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
> + OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);
> + OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff);
> + OS << static_cast<uint8_t>((Binary >> 0x10) & 0xff);
> + OS << static_cast<uint8_t>((Binary >> 0x18) & 0xff);
> +}
> +}
> +
> +HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
> + MCSubtargetInfo const &aMST,
> + MCContext &aMCT)
> + : MST(aMST), MCT(aMCT) {}
> +
> +void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI,
> raw_ostream &OS,
> + SmallVectorImpl<MCFixup>
> &Fixups,
> + MCSubtargetInfo const &STI)
> const {
> + HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
> + uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) |
> getPacketBits(HMB);
> + assert(HMB.getDesc().getSize() == 4 && "All instructions should be
> 32bit");
> + emitLittleEndian(Binary, OS);
> + ++MCNumEmitted;
> +}
> +
> +unsigned
> +HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const
> &MO,
> + SmallVectorImpl<MCFixup> &Fixups,
> + MCSubtargetInfo const &STI) const
> {
> + if (MO.isReg())
> + return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
> + if (MO.isImm())
> + return static_cast<unsigned>(MO.getImm());
> + llvm_unreachable("Only Immediates and Registers implemented right
> now");
> +}
> +
> +MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {
> + return MST;
> +}
> +
> +MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
> + MCRegisterInfo const
> &MRI,
> + MCSubtargetInfo const
> &MST,
> + MCContext &MCT) {
> + return new HexagonMCCodeEmitter(MII, MST, MCT);
> +}
> +
> +#include "HexagonGenMCCodeEmitter.inc"
>
> Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h?rev=218986&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
> (added)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h Fri
> Oct 3 08:18:11 2014
> @@ -0,0 +1,60 @@
> +//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++
> -*-===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +///
> +/// \file
> +/// \brief Definition for classes that emit Hexagon machine code from
> MCInsts
> +///
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef HEXAGONMCCODEEMITTER_H
> +#define HEXAGONMCCODEEMITTER_H
> +
> +#include "llvm/MC/MCCodeEmitter.h"
> +#include "llvm/MC/MCExpr.h"
> +#include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCInstrInfo.h"
> +#include "llvm/MC/MCRegisterInfo.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> +#include "llvm/Support/raw_ostream.h"
> +
> +namespace llvm {
> +
> +class HexagonMCCodeEmitter : public MCCodeEmitter {
> + MCSubtargetInfo const &MST;
> + MCContext &MCT;
> +
> +public:
> + HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const
> &aMST,
> + MCContext &aMCT);
> +
> + MCSubtargetInfo const &getSubtargetInfo() const;
> +
> + void EncodeInstruction(MCInst const &MI, raw_ostream &OS,
> + SmallVectorImpl<MCFixup> &Fixups,
> + MCSubtargetInfo const &STI) const override;
> +
> + // getBinaryCodeForInstr - TableGen'erated function for getting the
> + // binary encoding for an instruction.
> + uint64_t getBinaryCodeForInstr(MCInst const &MI,
> + SmallVectorImpl<MCFixup> &Fixups,
> + MCSubtargetInfo const &STI) const;
> +
> + /// \brief Return binary encoding of operand.
> + unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
> + SmallVectorImpl<MCFixup> &Fixups,
> + MCSubtargetInfo const &STI) const;
> +
> +private:
> + HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete;
> + void operator=(HexagonMCCodeEmitter const &) = delete;
> +}; // class HexagonMCCodeEmitter
> +
> +} // namespace llvm
> +
> +#endif /* HEXAGONMCCODEEMITTER_H */
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=218986&r1=218985&r2=218986&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Fri
> Oct 3 08:18:11 2014
> @@ -46,9 +46,8 @@ static MCRegisterInfo *createHexagonMCRe
> return X;
> }
>
> -static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT,
> - StringRef CPU,
> - StringRef FS) {
> +static MCSubtargetInfo *
> +createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
> MCSubtargetInfo *X = new MCSubtargetInfo();
> InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
> return X;
> @@ -59,16 +58,16 @@ static MCAsmInfo *createHexagonMCAsmInfo
> MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
>
> // VirtualFP = (R30 + #0).
> - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
> - nullptr, Hexagon::R30, 0);
> + MCCFIInstruction Inst =
> + MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
> MAI->addInitialFrameState(Inst);
>
> return MAI;
> }
>
> static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT,
> Reloc::Model RM,
> - CodeModel::Model CM,
> - CodeGenOpt::Level OL) {
> + CodeModel::Model CM,
> + CodeGenOpt::Level OL) {
> MCCodeGenInfo *X = new MCCodeGenInfo();
> // For the time being, use static relocations, since there's really no
> // support for PIC yet.
> @@ -86,7 +85,8 @@ extern "C" void LLVMInitializeHexagonTar
> createHexagonMCCodeGenInfo);
>
> // Register the MC instruction info.
> - TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
> createHexagonMCInstrInfo);
> + TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
> + createHexagonMCInstrInfo);
>
> // Register the MC register info.
> TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
> @@ -95,4 +95,8 @@ extern "C" void LLVMInitializeHexagonTar
> // Register the MC subtarget info.
> TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
> createHexagonMCSubtargetInfo);
> +
> + // Register the MC Code Emitter
Please add a period to the comment.
> + TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
> + createHexagonMCCodeEmitter);
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=218986&r1=218985&r2=218986&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Fri
> Oct 3 08:18:11 2014
> @@ -15,11 +15,20 @@
> #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
>
> namespace llvm {
> +class MCCodeEmitter;
> +class MCContext;
> +class MCInstrInfo;
> +class MCRegisterInfo;
> class MCSubtargetInfo;
> class Target;
>
> extern Target TheHexagonTarget;
>
> +MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
> + const MCRegisterInfo &MRI,
> + const MCSubtargetInfo &MST,
> + MCContext &MCT);
> +
> } // End llvm namespace
>
> // Define symbolic names for Hexagon registers. This defines a mapping
> from
>
> Modified: llvm/trunk/unittests/MC/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/CMakeLists.txt?rev=218986&r1=218985&r2=218986&view=diff
> ==============================================================================
> --- llvm/trunk/unittests/MC/CMakeLists.txt (original)
> +++ llvm/trunk/unittests/MC/CMakeLists.txt Fri Oct 3 08:18:11 2014
> @@ -7,3 +7,9 @@ add_llvm_unittest(MCTests
> StringTableBuilderTest.cpp
> YAMLTest.cpp
> )
> +
> +foreach(t ${LLVM_TARGETS_TO_BUILD})
> + if (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")
> + add_subdirectory(${t})
> + endif (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")
> +endforeach()
>
>
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