[llvm] r218802 - [x86] Sort the ISA-specific RUN lines for vector-sext.ll to go from
Chandler Carruth
chandlerc at gmail.com
Wed Oct 1 13:32:44 PDT 2014
Author: chandlerc
Date: Wed Oct 1 15:32:44 2014
New Revision: 218802
URL: http://llvm.org/viewvc/llvm-project?rev=218802&view=rev
Log:
[x86] Sort the ISA-specific RUN lines for vector-sext.ll to go from
oldest to newest. This makes more sense to me and is more consistent
with other tests.
Modified:
llvm/trunk/test/CodeGen/X86/vector-sext.ll
Modified: llvm/trunk/test/CodeGen/X86/vector-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-sext.ll?rev=218802&r1=218801&r2=218802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-sext.ll Wed Oct 1 15:32:44 2014
@@ -1,22 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
-; AVX1-LABEL: sext_8i16_to_8i32:
-; AVX1: ## BB#0:
-; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
-; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
-; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: sext_8i16_to_8i32:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
-; AVX2-NEXT: retq
-;
; SSE-LABEL: sext_8i16_to_8i32:
; SSE: ## BB#0:
; SSE-NEXT: movdqa %xmm0, %xmm1
@@ -28,25 +15,25 @@ define <8 x i32> @sext_8i16_to_8i32(<8 x
; SSE-NEXT: pslld $16, %xmm1
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: retq
-
- %B = sext <8 x i16> %A to <8 x i32>
- ret <8 x i32>%B
-}
-
-define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
-; AVX1-LABEL: sext_4i32_to_4i64:
+;
+; AVX1-LABEL: sext_8i16_to_8i32:
; AVX1: ## BB#0:
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: sext_4i32_to_4i64:
+; AVX2-LABEL: sext_8i16_to_8i32:
; AVX2: ## BB#0:
-; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
+; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: retq
-;
+
+ %B = sext <8 x i16> %A to <8 x i32>
+ ret <8 x i32>%B
+}
+
+define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
; SSE-LABEL: sext_4i32_to_4i64:
; SSE: ## BB#0:
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,1,0]
@@ -69,23 +56,36 @@ define <4 x i64> @sext_4i32_to_4i64(<4 x
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq
+;
+; AVX1-LABEL: sext_4i32_to_4i64:
+; AVX1: ## BB#0:
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: sext_4i32_to_4i64:
+; AVX2: ## BB#0:
+; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
+; AVX2-NEXT: retq
%B = sext <4 x i32> %A to <4 x i64>
ret <4 x i64>%B
}
define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
-; AVX-LABEL: load_sext_test1:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
-; AVX-NEXT: retq
-;
; SSE-LABEL: load_sext_test1:
; SSE: ## BB#0:
; SSE-NEXT: movq (%rdi), %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: retq
+;
+; AVX-LABEL: load_sext_test1:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <4 x i16>* %ptr
%Y = sext <4 x i16> %X to <4 x i32>
@@ -93,18 +93,6 @@ define <4 x i32> @load_sext_test1(<4 x i
}
define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
-; AVX-LABEL: load_sext_test2:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
-; AVX-NEXT: retq
-;
-; SSSE3-LABEL: load_sext_test2:
-; SSSE3: ## BB#0:
-; SSSE3-NEXT: movd (%rdi), %xmm0
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3]
-; SSSE3-NEXT: psrad $24, %xmm0
-; SSSE3-NEXT: retq
-;
; SSE2-LABEL: load_sext_test2:
; SSE2: ## BB#0:
; SSE2-NEXT: movl (%rdi), %eax
@@ -120,17 +108,24 @@ define <4 x i32> @load_sext_test2(<4 x i
; SSE2-NEXT: pinsrw $7, %edx, %xmm0
; SSE2-NEXT: psrad $24, %xmm0
; SSE2-NEXT: retq
+;
+; SSSE3-LABEL: load_sext_test2:
+; SSSE3: ## BB#0:
+; SSSE3-NEXT: movd (%rdi), %xmm0
+; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3]
+; SSSE3-NEXT: psrad $24, %xmm0
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: load_sext_test2:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <4 x i8>* %ptr
%Y = sext <4 x i8> %X to <4 x i32>
ret <4 x i32>%Y
}
define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
-; AVX-LABEL: load_sext_test3:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
-; AVX-NEXT: retq
-;
; SSE-LABEL: load_sext_test3:
; SSE: ## BB#0:
; SSE-NEXT: movsbq 1(%rdi), %rax
@@ -139,17 +134,17 @@ define <2 x i64> @load_sext_test3(<2 x i
; SSE-NEXT: movd %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
+;
+; AVX-LABEL: load_sext_test3:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <2 x i8>* %ptr
%Y = sext <2 x i8> %X to <2 x i64>
ret <2 x i64>%Y
}
define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
-; AVX-LABEL: load_sext_test4:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
-; AVX-NEXT: retq
-;
; SSE-LABEL: load_sext_test4:
; SSE: ## BB#0:
; SSE-NEXT: movswq 2(%rdi), %rax
@@ -158,17 +153,17 @@ define <2 x i64> @load_sext_test4(<2 x i
; SSE-NEXT: movd %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
+;
+; AVX-LABEL: load_sext_test4:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <2 x i16>* %ptr
%Y = sext <2 x i16> %X to <2 x i64>
ret <2 x i64>%Y
}
define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
-; AVX-LABEL: load_sext_test5:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
-; AVX-NEXT: retq
-;
; SSE-LABEL: load_sext_test5:
; SSE: ## BB#0:
; SSE-NEXT: movslq 4(%rdi), %rax
@@ -177,46 +172,34 @@ define <2 x i64> @load_sext_test5(<2 x i
; SSE-NEXT: movd %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
+;
+; AVX-LABEL: load_sext_test5:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <2 x i32>* %ptr
%Y = sext <2 x i32> %X to <2 x i64>
ret <2 x i64>%Y
}
define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
-; AVX-LABEL: load_sext_test6:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
-; AVX-NEXT: retq
-;
; SSE-LABEL: load_sext_test6:
; SSE: ## BB#0:
; SSE-NEXT: movq (%rdi), %xmm0
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: psraw $8, %xmm0
; SSE-NEXT: retq
+;
+; AVX-LABEL: load_sext_test6:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
+; AVX-NEXT: retq
%X = load <8 x i8>* %ptr
%Y = sext <8 x i8> %X to <8 x i16>
ret <8 x i16>%Y
}
define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
-; AVX1-LABEL: sext_4i1_to_4i64:
-; AVX1: ## BB#0:
-; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
-; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
-; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: sext_4i1_to_4i64:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
-; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
-; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
-; AVX2-NEXT: retq
-;
; SSE-LABEL: sext_4i1_to_4i64:
; SSE: ## BB#0:
; SSE-NEXT: pslld $31, %xmm0
@@ -241,26 +224,28 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq
- %extmask = sext <4 x i1> %mask to <4 x i64>
- ret <4 x i64> %extmask
-}
-
-define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
-; AVX1-LABEL: sext_16i8_to_16i16:
+;
+; AVX1-LABEL: sext_4i1_to_4i64:
; AVX1: ## BB#0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vpmovsxbw %xmm0, %xmm1
+; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
+; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
-; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: sext_16i8_to_16i16:
+; AVX2-LABEL: sext_4i1_to_4i64:
; AVX2: ## BB#0:
-; AVX2-NEXT: vmovdqa (%rdi), %xmm0
-; AVX2-NEXT: vpmovsxbw %xmm0, %ymm0
+; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
+; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
+; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
; AVX2-NEXT: retq
-;
+ %extmask = sext <4 x i1> %mask to <4 x i64>
+ ret <4 x i64> %extmask
+}
+
+define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
; SSE-LABEL: sext_16i8_to_16i16:
; SSE: ## BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
@@ -272,29 +257,27 @@ define <16 x i16> @sext_16i8_to_16i16(<1
; SSE-NEXT: psllw $8, %xmm1
; SSE-NEXT: psraw $8, %xmm1
; SSE-NEXT: retq
- %X = load <16 x i8>* %ptr
- %Y = sext <16 x i8> %X to <16 x i16>
- ret <16 x i16> %Y
-}
-
-define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
-; AVX1-LABEL: sext_4i8_to_4i64:
+;
+; AVX1-LABEL: sext_16i8_to_16i16:
; AVX1: ## BB#0:
-; AVX1-NEXT: vpslld $24, %xmm0, %xmm0
-; AVX1-NEXT: vpsrad $24, %xmm0, %xmm0
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; AVX1-NEXT: vmovdqa (%rdi), %xmm0
+; AVX1-NEXT: vpmovsxbw %xmm0, %xmm1
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: sext_4i8_to_4i64:
+; AVX2-LABEL: sext_16i8_to_16i16:
; AVX2: ## BB#0:
-; AVX2-NEXT: vpslld $24, %xmm0, %xmm0
-; AVX2-NEXT: vpsrad $24, %xmm0, %xmm0
-; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
+; AVX2-NEXT: vmovdqa (%rdi), %xmm0
+; AVX2-NEXT: vpmovsxbw %xmm0, %ymm0
; AVX2-NEXT: retq
-;
+ %X = load <16 x i8>* %ptr
+ %Y = sext <16 x i8> %X to <16 x i16>
+ ret <16 x i16> %Y
+}
+
+define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
; SSE-LABEL: sext_4i8_to_4i64:
; SSE: ## BB#0:
; SSE-NEXT: pslld $24, %xmm0
@@ -319,49 +302,28 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq
- %extmask = sext <4 x i8> %mask to <4 x i64>
- ret <4 x i64> %extmask
-}
-
-define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
-; AVX1-LABEL: load_sext_4i8_to_4i64:
+;
+; AVX1-LABEL: sext_4i8_to_4i64:
; AVX1: ## BB#0:
-; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0
+; AVX1-NEXT: vpslld $24, %xmm0, %xmm0
+; AVX1-NEXT: vpsrad $24, %xmm0, %xmm0
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: load_sext_4i8_to_4i64:
+; AVX2-LABEL: sext_4i8_to_4i64:
; AVX2: ## BB#0:
-; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0
+; AVX2-NEXT: vpslld $24, %xmm0, %xmm0
+; AVX2-NEXT: vpsrad $24, %xmm0, %xmm0
+; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
; AVX2-NEXT: retq
-;
-; SSSE3-LABEL: load_sext_4i8_to_4i64:
-; SSSE3: ## BB#0:
-; SSSE3-NEXT: movd (%rdi), %xmm1
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
-; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,1,0]
-; SSSE3-NEXT: movd %xmm2, %rax
-; SSSE3-NEXT: movsbq %al, %rax
-; SSSE3-NEXT: movd %rax, %xmm0
-; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
-; SSSE3-NEXT: movd %xmm2, %rax
-; SSSE3-NEXT: movsbq %al, %rax
-; SSSE3-NEXT: movd %rax, %xmm2
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,0,3,0]
-; SSSE3-NEXT: movd %xmm2, %rax
-; SSSE3-NEXT: movsbq %al, %rax
-; SSSE3-NEXT: movd %rax, %xmm1
-; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
-; SSSE3-NEXT: movd %xmm2, %rax
-; SSSE3-NEXT: movsbq %al, %rax
-; SSSE3-NEXT: movd %rax, %xmm2
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; SSSE3-NEXT: retq
-;
+ %extmask = sext <4 x i8> %mask to <4 x i64>
+ ret <4 x i64> %extmask
+}
+
+define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
; SSE2-LABEL: load_sext_4i8_to_4i64:
; SSE2: ## BB#0:
; SSE2-NEXT: movl (%rdi), %eax
@@ -392,26 +354,50 @@ define <4 x i64> @load_sext_4i8_to_4i64(
; SSE2-NEXT: movd %rax, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE2-NEXT: retq
- %X = load <4 x i8>* %ptr
- %Y = sext <4 x i8> %X to <4 x i64>
- ret <4 x i64>%Y
-}
-
-define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
-; AVX1-LABEL: load_sext_4i16_to_4i64:
+;
+; SSSE3-LABEL: load_sext_4i8_to_4i64:
+; SSSE3: ## BB#0:
+; SSSE3-NEXT: movd (%rdi), %xmm1
+; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,1,0]
+; SSSE3-NEXT: movd %xmm2, %rax
+; SSSE3-NEXT: movsbq %al, %rax
+; SSSE3-NEXT: movd %rax, %xmm0
+; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
+; SSSE3-NEXT: movd %xmm2, %rax
+; SSSE3-NEXT: movsbq %al, %rax
+; SSSE3-NEXT: movd %rax, %xmm2
+; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,0,3,0]
+; SSSE3-NEXT: movd %xmm2, %rax
+; SSSE3-NEXT: movsbq %al, %rax
+; SSSE3-NEXT: movd %rax, %xmm1
+; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
+; SSSE3-NEXT: movd %xmm2, %rax
+; SSSE3-NEXT: movsbq %al, %rax
+; SSSE3-NEXT: movd %rax, %xmm2
+; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSSE3-NEXT: retq
+;
+; AVX1-LABEL: load_sext_4i8_to_4i64:
; AVX1: ## BB#0:
-; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
+; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: load_sext_4i16_to_4i64:
+; AVX2-LABEL: load_sext_4i8_to_4i64:
; AVX2: ## BB#0:
-; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0
+; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0
; AVX2-NEXT: retq
-;
+ %X = load <4 x i8>* %ptr
+ %Y = sext <4 x i8> %X to <4 x i64>
+ ret <4 x i64>%Y
+}
+
+define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
; SSE-LABEL: load_sext_4i16_to_4i64:
; SSE: ## BB#0:
; SSE-NEXT: movq (%rdi), %xmm1
@@ -435,6 +421,20 @@ define <4 x i64> @load_sext_4i16_to_4i64
; SSE-NEXT: movd %rax, %xmm2
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
+;
+; AVX1-LABEL: load_sext_4i16_to_4i64:
+; AVX1: ## BB#0:
+; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
+; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: load_sext_4i16_to_4i64:
+; AVX2: ## BB#0:
+; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0
+; AVX2-NEXT: retq
%X = load <4 x i16>* %ptr
%Y = sext <4 x i16> %X to <4 x i64>
ret <4 x i64>%Y
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