[PATCH] [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)

Oliver Stannard oliver.stannard at arm.com
Tue Sep 30 01:54:02 PDT 2014


The Cortex-M7 has 3 options for it's FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features.

http://reviews.llvm.org/D5536

Files:
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMAsmPrinter.cpp
  lib/Target/ARM/ARMFPUName.def
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  test/CodeGen/ARM/build-attributes.ll
  test/CodeGen/Thumb2/cortex-fp.ll
  test/CodeGen/Thumb2/float-cmp.ll
  test/CodeGen/Thumb2/float-intrinsics-double.ll
  test/CodeGen/Thumb2/float-intrinsics-float.ll
  test/CodeGen/Thumb2/float-ops.ll
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