[llvm] r218560 - Fix TableGen -gen-disassembler output for bit fields with an offset.
Craig Topper
craig.topper at gmail.com
Fri Sep 26 21:38:02 PDT 2014
Author: ctopper
Date: Fri Sep 26 23:38:02 2014
New Revision: 218560
URL: http://llvm.org/viewvc/llvm-project?rev=218560&view=rev
Log:
Fix TableGen -gen-disassembler output for bit fields with an offset.
This fixes bit assignments like this
Inst{7-0} = Foo{9-2}
Patch by Steve King.
Added:
llvm/trunk/test/TableGen/BitOffsetDecoder.td
Modified:
llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
Added: llvm/trunk/test/TableGen/BitOffsetDecoder.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/BitOffsetDecoder.td?rev=218560&view=auto
==============================================================================
--- llvm/trunk/test/TableGen/BitOffsetDecoder.td (added)
+++ llvm/trunk/test/TableGen/BitOffsetDecoder.td Fri Sep 26 23:38:02 2014
@@ -0,0 +1,74 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+ let InstructionSet = archInstrInfo;
+}
+
+def Myi32 : Operand<i32> {
+ let DecoderMethod = "DecodeMyi32";
+}
+
+
+let OutOperandList = (outs), Size = 2 in {
+
+def foo : Instruction {
+ let InOperandList = (ins i32imm:$factor);
+ field bits<16> Inst;
+ bits<32> factor;
+ let Inst{7-0} = 0xAA;
+ let Inst{14-8} = factor{6-0}; // no offset
+ let AsmString = "foo $factor";
+ field bits<16> SoftFail = 0;
+ }
+
+def bar : Instruction {
+ let InOperandList = (ins i32imm:$factor);
+ field bits<16> Inst;
+ bits<32> factor;
+ let Inst{7-0} = 0xBB;
+ let Inst{15-8} = factor{10-3}; // offset by 3
+ let AsmString = "bar $factor";
+ field bits<16> SoftFail = 0;
+ }
+
+def biz : Instruction {
+ let InOperandList = (ins i32imm:$factor);
+ field bits<16> Inst;
+ bits<32> factor;
+ let Inst{7-0} = 0xCC;
+ let Inst{11-8,15-12} = factor{10-3}; // offset by 3, multipart
+ let AsmString = "biz $factor";
+ field bits<16> SoftFail = 0;
+ }
+
+def baz : Instruction {
+ let InOperandList = (ins Myi32:$factor);
+ field bits<16> Inst;
+ bits<32> factor;
+ let Inst{7-0} = 0xDD;
+ let Inst{15-8} = factor{11-4}; // offset by 4 + custom decode
+ let AsmString = "baz $factor";
+ field bits<16> SoftFail = 0;
+ }
+
+def bum : Instruction {
+ let InOperandList = (ins i32imm:$factor);
+ field bits<16> Inst;
+ bits<32> factor;
+ let Inst{7-0} = 0xEE;
+ let Inst{15-8} = !srl(factor,5);
+ let AsmString = "bum $factor";
+ field bits<16> SoftFail = 0;
+ }
+}
+
+
+// CHECK: tmp = fieldFromInstruction(insn, 8, 7);
+// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 3;
+// CHECK: tmp |= (fieldFromInstruction(insn, 8, 4) << 7);
+// CHECK: tmp |= (fieldFromInstruction(insn, 12, 4) << 3);
+// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 4;
\ No newline at end of file
Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=218560&r1=218559&r2=218560&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Fri Sep 26 23:38:02 2014
@@ -1051,7 +1051,11 @@ void FilterChooser::emitBinaryParser(raw
OperandInfo::const_iterator OI = OpInfo.begin();
o.indent(Indentation) << "tmp = fieldFromInstruction"
<< "(insn, " << OI->Base << ", " << OI->Width
- << ");\n";
+ << ")";
+ if (OI->Offset)
+ o << " << " << OI->Offset;
+ o << ";\n";
+
} else {
o.indent(Indentation) << "tmp = 0;\n";
for (OperandInfo::const_iterator OI = OpInfo.begin(), OE = OpInfo.end();
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