[llvm] r218534 - R600/SI: Add a note about the order of the operands to div_scale
Matt Arsenault
Matthew.Arsenault at amd.com
Fri Sep 26 10:55:09 PDT 2014
Author: arsenm
Date: Fri Sep 26 12:55:09 2014
New Revision: 218534
URL: http://llvm.org/viewvc/llvm-project?rev=218534&view=rev
Log:
R600/SI: Add a note about the order of the operands to div_scale
Modified:
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=218534&r1=218533&r2=218534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Fri Sep 26 12:55:09 2014
@@ -825,6 +825,12 @@ SDValue AMDGPUTargetLowering::LowerINTRI
// first parameter must be the same as the first instruction.
SDValue Numerator = Op.getOperand(1);
SDValue Denominator = Op.getOperand(2);
+
+ // Note this order is opposite of the machine instruction's operations,
+ // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
+ // intrinsic has the numerator as the first operand to match a normal
+ // division operation.
+
SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
More information about the llvm-commits
mailing list