[PATCH] x86 avx: add isel pattern for (v2f64 (X86VBroadcast f64:$src))

[Akira Hatanaka]

My comment didn't make sense.

I meant to say we used to have to use register classes and have tablegen
infer the type, but we can now directly specify the type instead.

On Thu, Sep 25, 2014 at 11:50 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:

> You can use either one. We used to have to use register classes and have
> tablegen infer the type, but that changed some time ago, and tablegen can
> now find out type f64 should be used for FR64.
>
> On Thu, Sep 25, 2014 at 9:11 AM, Sanjay Patel <spatel at rotateright.com>
> wrote:
>
>> Hi all -
>>
>> In this patch we use the "f64" value type for the source op in the
>> pattern. The existing patterns that are similar use the "FR64" register
>> class. Eg:
>>     def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
>>               (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
>>
>> Is there any functional difference or preference for this specification
>> one way or the other?
>>
>>
>> On Wed, Sep 24, 2014 at 6:39 PM, Akira Hatanaka <ahatanak at gmail.com>
>> wrote:
>>
>>> Thanks, committed in r218431.
>>>
>>> On Wed, Sep 24, 2014 at 5:28 PM, Chandler Carruth <chandlerc at google.com>
>>> wrote:
>>>
>>>> LGTM.
>>>>
>>>> On Wed, Sep 24, 2014 at 5:21 PM, Akira Hatanaka <ahatanak at gmail.com>
>>>> wrote:
>>>>
>>>>> The attached patch adds a pattern for X86Broadcast. This is the error
>>>>> message I'm currently seeing when I compile the test case:
>>>>>
>>>>>
>>>>> LLVM ERROR: Cannot select: 0x7fda11827200: v2f64 = X86ISD::VBROADCAST
>>>>> 0x7fda12024918 [ORD=2] [ID=14]
>>>>>
>>>>>   0x7fda12024918: f64,ch = load 0x7fda1150bcd0, 0x7fda12024600,
>>>>> 0x7fda12025050<LD8[ConstantPool]> [ORD=2] [ID=12]
>>>>>
>>>>>     0x7fda12024600: i64 = X86ISD::WrapperRIP 0x7fda12024c30 [ID=10]
>>>>>
>>>>>       0x7fda12024c30: i64 = TargetConstantPool<double -1.000000e+00> 0
>>>>> [ID=8]
>>>>>
>>>>>     0x7fda12025050: i64 = undef [ID=2]
>>>>>
>>>>> This fixes PR21050.
>>>>>
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>>>>>
>>>>>
>>>>
>>>
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>
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