[llvm] r218441 - [x86] Rearrange the code for v16i16 lowering a bit for clarity and to

[Chandler Carruth]

Author: chandlerc
Date: Wed Sep 24 23:03:22 2014
New Revision: 218441

URL: http://llvm.org/viewvc/llvm-project?rev=218441&view=rev
Log:
[x86] Rearrange the code for v16i16 lowering a bit for clarity and to
reduce the amount of checking we do here.

The first realization is that only non-crossing cases between 128-bit
lanes are handled by almost the entire function. It makes more sense to
handle the crossing cases first.

THe second is that until we actually are going to generate fancy shared
lowering strategies that use the repeated semantics of the v8i16
lowering, we should waste time checking for repeated masks. It is
simplest to directly test for the entire unpck masks anyways, so we
gained nothing from this.

This also matches the structure of v32i8 more closely.

No functionality changed here.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=218441&r1=218440&r2=218441&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 24 23:03:22 2014
@@ -9617,35 +9617,6 @@ static SDValue lowerV16I16VectorShuffle(
   assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
   assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
 
-  if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
-                                                Subtarget, DAG))
-    return Blend;
-
-  // If the shuffle mask is repeated in each 128-bit lane we can use more
-  // efficient instructions that mirror the shuffles across the two 128-bit
-  // lanes.
-  SmallVector<int, 4> RepeatedMask;
-  if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
-    assert(RepeatedMask.size() == 8 && "Unexpected repeated mask size!");
-    // FIXME: It might be worth it to call into the (terribly complex) v8i16
-    // lowering here.
-
-    // Use dedicated unpack instructions for masks that match their pattern.
-    //
-    if (isShuffleEquivalent(Mask,
-                            // First 128-bit lane:
-                            0, 16, 1, 17, 2, 18, 3, 19,
-                            // Second 128-bit lane:
-                            8, 24, 9, 25, 10, 26, 11, 27))
-      return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
-    if (isShuffleEquivalent(Mask,
-                            // First 128-bit lane:
-                            4,  20, 5,  21, 6, 22, 7, 23,
-                            // Second 128-bit lane:
-                            12, 28, 13, 29, 14, 30, 15, 31))
-      return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
-  }
-
   // There are no generalized cross-lane shuffle operations available on i16
   // element types.
   // FIXME: We should teach the "split and lower" path to do something more
@@ -9661,6 +9632,24 @@ static SDValue lowerV16I16VectorShuffle(
   if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
     return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
 
+  if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
+                                                Subtarget, DAG))
+    return Blend;
+
+  // Use dedicated unpack instructions for masks that match their pattern.
+  if (isShuffleEquivalent(Mask,
+                          // First 128-bit lane:
+                          0, 16, 1, 17, 2, 18, 3, 19,
+                          // Second 128-bit lane:
+                          8, 24, 9, 25, 10, 26, 11, 27))
+    return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
+  if (isShuffleEquivalent(Mask,
+                          // First 128-bit lane:
+                          4, 20, 5, 21, 6, 22, 7, 23,
+                          // Second 128-bit lane:
+                          12, 28, 13, 29, 14, 30, 15, 31))
+    return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
+
   if (isSingleInputShuffleMask(Mask)) {
     SDValue PSHUFBMask[32];
     for (int i = 0; i < 16; ++i) {