[PATCH] [AArch64] Enable partial unrolling and runtime unrolling for AArch64 target

[Eric Christopher]

On Mon, Sep 22, 2014 at 10:10 AM, Eric Christopher <echristo at gmail.com> wrote:
> Looks like the chip itself has a 32 entry loop buffer (with 2 forward and one backward branch support). What range of values did you check here? (i.e. why is 32 not the right value to put here like with the other port specific constants?)
>

FYI just wanted to mention where I got this information which may not
be correct - it seems to have it down as a clone of the A15 and isn't
representative of the actual silicon here.

http://pc.watch.impress.co.jp/video/pcw/docs/614/543/08p.pdf

for the first bit, which looks like it's based on this article:

http://pc.watch.impress.co.jp/docs/column/kaigai/20121031_569691.html

If we're just going to go with a heuristics based approach, it might
be nice to show some samples/graphs and definitely comment that in the
code with how it was determined.

-eric