[PATCH 1/1] DAGCombiner: Add (A - (0-B)) -> A+B optimization

[Jan Vesely]

On Tue, 2014-09-23 at 18:24 -0700, Matt Arsenault wrote:
> On Sep 23, 2014, at 6:05 PM, Jan Vesely <jan.vesely at rutgers.edu> wrote:
> 
> > On Tue, 2014-09-23 at 15:21 -0400, Chad Rosier wrote:
> >> Testcase?
> > 
> > I'm not sure how to add one. The situation is tested in
> > test/Transforms/InstCombine/sub.ll (test4) and indeed "opt -instcombine"
> > work even without the patch.
> > Is there a way to test DAGCombiner in a similar (generic) way, or do I
> > need to add a backend specific test?
> 
> You usually need to add a target specific test for these kinds of things
> 
> > 
> > It's not clear to me why the instcombine and DAG combine nedd both to do
> > this kind of optimization.
> 
> There are lots of reasons this pattern would only be exposed during
> instruction selection, such as if a target custom lowered an operation
> which emitted this pattern

Thanks for the explanation (I think) I get the different roles of inst
combiner and dag combiner now. I still think it would be nice if there
was a way for them to share code so the patterns don't have to be
implemented twice.

the patch with tightened R600 add64 tests is attached. note that this
patch now needs to be applied on top of the two I sent earlier.

jan

> 
> 
> > 
> > jan
> > 
> >> 
> >>> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> >>> ---
> >>> lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++++
> >>> 1 file changed, 4 insertions(+)
> >>> 
> >>> diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> >>> b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> >>> index 33e7059..bc39fe3 100644
> >>> --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> >>> +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> >>> @@ -1794,6 +1794,10 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
> >>>   // fold (A+B)-B -> A
> >>>   if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
> >>>     return N0.getOperand(0);
> >>> +  // fold (A - (0-B)) -> A+B
> >>> +  if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0))
> >>> &&
> >>> +      cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
> >>> +    return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1.getOperand(1));
> >>>   // fold C2-(A+C1) -> (C2-C1)-A
> >>>   if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
> >>>     SDValue NewC = DAG.getConstant(N0C->getAPIntValue() -
> >>> N1C1->getAPIntValue(),
> >>> --
> >>> 1.9.3
> >>> 
> >>> _______________________________________________
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> >>> llvm-commits at cs.uiuc.edu
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> >>> 
> >> 
> >> 
> > 
> > -- 
> > Jan Vesely <jan.vesely at rutgers.edu>
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

-- 
Jan Vesely <jan.vesely at rutgers.edu>
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