[PATCH] [PATCH]Select wide immediate offset into [Base+XReg] addressing mode

[Hao Liu]

Hi t.p.northover,

Hi Tim and other reviewers,

A base register plus a wide immediate offset may not be encoded by [Base+immediate] addressing mode or ADD/SUB instructions. Currently it will be selected into [Base+0] addressing mode and generate following instructions:
     MOV  X0, WideImmediate
     ADD  X1, BaseReg, X0
     LDR  X2, [X1, 0]
But actually we can save one ADD by generating following instructions:
     MOV  X0, WideImmediate
     LDR  X2, [BaseReg, X0]

Review please.

Thanks,
-Hao

http://reviews.llvm.org/D5477

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll
  test/CodeGen/AArch64/arm64-addrmode.ll
  test/CodeGen/AArch64/fast-isel-addressing-modes.ll
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