[PATCH] Transform 3 operand instructions to 2 operand versions of the same instruction if first 2 register operands are the same for thumb1

[Renato Golin]

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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:5655
@@ +5654,3 @@
+        Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
+      ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[3]);
+      ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[4]);
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Either call these Reg1, Reg2 or Op3, Op4.

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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:5666
@@ +5665,3 @@
+          if (!Op3.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
+              Operands.erase(Operands.begin() + 4);
+              if (Mnemonic == "add" && !CarrySetting) {
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Being pedantic, the ARM ARM refers to the first register as being optional, not the second. :)

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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:5670
@@ +5669,3 @@
+                  // remove the CCOut operand as well.
+                  Operands.erase(Operands.begin() + 1);
+              }
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why is this necessary?

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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:5686
@@ +5685,3 @@
+     static_cast<ARMOperand &>(*Operands[2]).getReg() ==
+     static_cast<ARMOperand &>(*Operands[3]).getReg()) {
+        Operands.erase(Operands.begin() + 2);
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You could simplify this with a nested if

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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:8196
@@ -8151,3 +8195,3 @@
   // to be from r0-r7 when in Thumb2.
-  else if (Opc == ARM::tADDhirr && isThumbOne() &&
+  else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
            isARMLowRegister(Inst.getOperand(1).getReg()) &&
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Can you describe why is this change needed?

http://reviews.llvm.org/D5463