[llvm] r218356 - R600/SI: Fix weird CHECK-DAG usage

[Matt Arsenault]

Author: arsenm
Date: Tue Sep 23 21:14:26 2014
New Revision: 218356

URL: http://llvm.org/viewvc/llvm-project?rev=218356&view=rev
Log:
R600/SI: Fix weird CHECK-DAG usage

This prevents these from failing in a future commit.

Modified:
    llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
    llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll

Modified: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll?rev=218356&r1=218355&r2=218356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll Tue Sep 23 21:14:26 2014
@@ -6,9 +6,9 @@ declare double @llvm.AMDGPU.div.fixup.f6
 ; SI-LABEL: @test_div_fixup_f32:
 ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]]
 ; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]]
+; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]]
+; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]]
 ; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
 ; SI: BUFFER_STORE_DWORD [[RESULT]],
 ; SI: S_ENDPGM

Modified: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll?rev=218356&r1=218355&r2=218356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll Tue Sep 23 21:14:26 2014
@@ -6,9 +6,9 @@ declare double @llvm.AMDGPU.div.fmas.f64
 ; SI-LABEL: @test_div_fmas_f32:
 ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]]
 ; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]]
+; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]]
+; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]]
 ; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
 ; SI: BUFFER_STORE_DWORD [[RESULT]],
 ; SI: S_ENDPGM