PATCH: R600: 64-bit division
Tom Stellard
tom at stellard.net
Tue Sep 23 13:47:09 PDT 2014
On Fri, Sep 19, 2014 at 02:47:13PM -0400, Matt Arsenault wrote:
>
> >0003-R600-SI-Use-isOperandLegal-to-simplify-legalization-.patch
> >
> >
> > From 835d8f79d0491611566ac124fe072f8f85723cb3 Mon Sep 17 00:00:00 2001
> >From: Tom Stellard<thomas.stellard at amd.com>
> >Date: Tue, 16 Sep 2014 09:19:11 -0400
> >Subject: [PATCH 3/8] R600/SI: Use isOperandLegal() to simplify legalization of
> > VOP3 instructions
> >
> >---
> > lib/Target/R600/SIInstrInfo.cpp | 27 +++------------------------
> > 1 file changed, 3 insertions(+), 24 deletions(-)
> >
> >diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> >index 294aa70..1b90d41 100644
> >--- a/lib/Target/R600/SIInstrInfo.cpp
> >+++ b/lib/Target/R600/SIInstrInfo.cpp
> >@@ -1174,33 +1174,12 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
> > // Legalize VOP3
> > if (isVOP3(MI->getOpcode())) {
> > int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
> >- unsigned SGPRReg = AMDGPU::NoRegister;
> > for (unsigned i = 0; i < 3; ++i) {
> > int Idx = VOP3Idx[i];
> >- if (Idx == -1)
> >- continue;
> >- MachineOperand &MO = MI->getOperand(Idx);
> >-
> >- if (MO.isReg()) {
> >- if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
> >- continue; // VGPRs are legal
> >-
> >- assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
> >-
> >- if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
> >- SGPRReg = MO.getReg();
> >- // We can use one SGPR in each VOP3 instruction.
> >- continue;
> >- }
> This looks like it checks that only one SGPR is used, but I don't
> think isOperandLegal can do that only looking at one operand. This
> loop could also be improved to find the operand that requires the
> fewest moves (e.g. inst s0, s1, s1 I think would end up finding s0
> first and inserting moves for both copies of s1)
>
Hi,
I have a patch called: "Clean up checks for legality of immediate operands"
which you reviewed, but I haven't committed yet which updates isOperandLegal
to check all operands. I also added a FIXME comment noting the inefficiency
you mentioned. Though, the new isOperandLegal handles your example, so I used
a different one: inst s0 s1 s0.
> >- } else if (!isLiteralConstant(MO)) {
> >- // If it is not a register and not a literal constant, then it must be
> >- // an inline constant which is always legal.
> >- continue;
> >- }
> >- // If we make it this far, then the operand is not legal and we must
> >- // legalize it.
> >- legalizeOpWithMove(MI, Idx);
> >+ if (Idx != -1 && !isOperandLegal(MI, Idx))
> >+ legalizeOpWithMove(MI, Idx);
> > }
> >+ return;
> > }
> > // Legalize REG_SEQUENCE and PHI
> >-- 1.8.5.5
> >
> >
> >0005-R600-SI-Add-pattern-for-i64-ctlz_zero_undef.patch
> >
> >
> > From 5600b629eb48753641ffac3cc73279b42e547e46 Mon Sep 17 00:00:00 2001
> >From: Tom Stellard<thomas.stellard at amd.com>
> >Date: Tue, 16 Sep 2014 09:18:31 -0400
> >Subject: [PATCH 5/8] R600/SI: Add pattern for i64 ctlz_zero_undef
> >
> >---
> > lib/Target/R600/SIInstrInfo.cpp | 127 +++++++++++++++++++++++++++++++++--
> > lib/Target/R600/SIInstrInfo.h | 9 +++
> > lib/Target/R600/SIInstructions.td | 24 +++++--
> > test/CodeGen/R600/ctlz_zero_undef.ll | 33 +++++++++
> > 4 files changed, 182 insertions(+), 11 deletions(-)
> >
> >diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> >index 1b90d41..ae9cbe9 100644
> >--- a/lib/Target/R600/SIInstrInfo.cpp
> >+++ b/lib/Target/R600/SIInstrInfo.cpp
> >@@ -510,7 +510,12 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
> > // This is just a placeholder for register allocation.
> > MI->eraseFromParent();
> > break;
> >+
> >+ case AMDGPU::S_CTLZ_ZERO_UNDEF_B32_B64:
> >+ MI->setDesc(get(AMDGPU::S_FLBIT_I32_B64));
> >+ return false;
> > }
> >+
> > return true;
> > }
> >@@ -1556,6 +1561,19 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
> > }
> > }
> >+void SIInstrInfo::getUsesToMoveToVALU(unsigned Reg,
> >+ const MachineRegisterInfo &MRI,
> >+ SmallVectorImpl<MachineInstr *> &Worklist) const {
> >+
> >+ for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
> >+ E = MRI.use_end(); I != E; ++I) {
>
> I think you can use range loop with MRI.use_operands(Reg) instead
Use operands only gives you a MachineOperand, but I need the iterator to
get the operand number.
> >+ MachineInstr &UseMI = *I->getParent();
> >+ if (!canReadVGPR(UseMI, I.getOperandNo())) {
> >+ Worklist.push_back(&UseMI);
> >+ }
> >+ }
> >+}
> >+
Attached are an updated set of patches.
-Tom
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