[llvm] r218190 - [x86] Teach the new vector shuffle lowering to use the AVX VPERMILPS
Chandler Carruth
chandlerc at gmail.com
Sat Sep 20 13:52:07 PDT 2014
Author: chandlerc
Date: Sat Sep 20 15:52:07 2014
New Revision: 218190
URL: http://llvm.org/viewvc/llvm-project?rev=218190&view=rev
Log:
[x86] Teach the new vector shuffle lowering to use the AVX VPERMILPS
instruction for single-vector floating point shuffles. This in turn
allows the shuffles to fold a load into the instruction which is one of
the common regressions hit with the new shuffle lowering.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=218190&r1=218189&r2=218190&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Sep 20 15:52:07 2014
@@ -7772,11 +7772,19 @@ static SDValue lowerV4F32VectorShuffle(S
int NumV2Elements =
std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
- if (NumV2Elements == 0)
- // Straight shuffle of a single input vector. We pass the input vector to
- // both operands to simulate this with a SHUFPS.
+ if (NumV2Elements == 0) {
+ if (Subtarget->hasAVX()) {
+ // If we have AVX, we can use VPERMILPS which will allow folding a load
+ // into the shuffle.
+ return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
+ getV4X86ShuffleImm8ForMask(Mask, DAG));
+ }
+
+ // Otherwise, use a straight shuffle of a single input vector. We pass the
+ // input vector to both operands to simulate this with a SHUFPS.
return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
getV4X86ShuffleImm8ForMask(Mask, DAG));
+ }
// Use dedicated unpack instructions for masks that match their pattern.
if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll?rev=218190&r1=218189&r2=218190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll Sat Sep 20 15:52:07 2014
@@ -73,51 +73,93 @@ define <4 x i32> @shuffle_v4i32_2121(<4
}
define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_0001
-; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_0001
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_0001
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,0,1]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_0020
-; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_0020
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_0020
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,2,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_0300
-; ALL: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_0300
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_0300
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,3,0,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_1000
-; ALL: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_1000
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_1000
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[1,0,0,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_2200
-; ALL: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_2200
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_2200
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[2,2,0,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_3330
-; ALL: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_3330
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_3330
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,3,3,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
-; ALL-LABEL: @shuffle_v4f32_3210
-; ALL: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
-; ALL-NEXT: retq
+; SSE-LABEL: @shuffle_v4f32_3210
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_v4f32_3210
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,2,1,0]
+; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %shuffle
}
@@ -805,3 +847,19 @@ define <4 x float> @insert_mem_and_zero_
%shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
ret <4 x float> %shuffle
}
+
+define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
+; SSE-LABEL: @shuffle_mem_v4f32_3210
+; SSE: # BB#0:
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: @shuffle_mem_v4f32_3210
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*}} # xmm0 = mem[3,2,1,0]
+; AVX-NEXT: retq
+ %a = load <4 x float>* %ptr
+ %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x float> %shuffle
+}
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