[PATCH 1/2] R600/SI: Add enums for some hard-coded values
Matt Arsenault
arsenm2 at gmail.com
Fri Sep 19 12:52:22 PDT 2014
On Sep 19, 2014, at 2:20 PM, Tom Stellard <thomas.stellard at amd.com> wrote:
> ---
> lib/Target/R600/SIISelLowering.cpp | 80 ++++++++++++++++++++++++++------------
> lib/Target/R600/SIInstrInfo.h | 19 +++++++++
> lib/Target/R600/SIRegisterInfo.cpp | 8 ++++
> lib/Target/R600/SIRegisterInfo.h | 6 ++-
> 4 files changed, 87 insertions(+), 26 deletions(-)
>
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 6d76685..10b4275 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -375,13 +375,17 @@ SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
> SDLoc SL, SDValue Chain,
> unsigned Offset, bool Signed) const {
> const DataLayout *DL = getDataLayout();
> + MachineFunction &MF = DAG.getMachineFunction();
> + const SIRegisterInfo *TRI =
> + static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
> + unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
>
> Type *Ty = VT.getTypeForEVT(*DAG.getContext());
>
> MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
> PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
> SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
> - MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
> + MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
> SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
> DAG.getConstant(Offset, MVT::i64));
> SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
> @@ -403,8 +407,9 @@ SDValue SITargetLowering::LowerFormalArguments(
> SDLoc DL, SelectionDAG &DAG,
> SmallVectorImpl<SDValue> &InVals) const {
>
> - const TargetRegisterInfo *TRI =
> - getTargetMachine().getSubtargetImpl()->getRegisterInfo();
> + const TargetMachine &TM = getTargetMachine();
> + const SIRegisterInfo *TRI =
> + static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
>
> MachineFunction &MF = DAG.getMachineFunction();
> FunctionType *FType = MF.getFunction()->getFunctionType();
> @@ -472,12 +477,27 @@ SDValue SITargetLowering::LowerFormalArguments(
> // The pointer to the scratch buffer is stored in SGPR2, SGPR3
> if (Info->getShaderType() == ShaderType::COMPUTE) {
> Info->NumUserSGPRs = 4;
> - CCInfo.AllocateReg(AMDGPU::SGPR0);
> - CCInfo.AllocateReg(AMDGPU::SGPR1);
> - CCInfo.AllocateReg(AMDGPU::SGPR2);
> - CCInfo.AllocateReg(AMDGPU::SGPR3);
> - MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
> - MF.addLiveIn(AMDGPU::SGPR2_SGPR3, &AMDGPU::SReg_64RegClass);
> +
> + unsigned InputPtrReg =
> + TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
> + unsigned InputPtrRegLo =
> + TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
> + unsigned InputPtrRegHi =
> + TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
> +
> + unsigned ScratchPtrReg =
> + TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
> + unsigned ScratchPtrRegLo =
> + TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
> + unsigned ScratchPtrRegHi =
> + TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
> +
> + CCInfo.AllocateReg(InputPtrRegLo);
> + CCInfo.AllocateReg(InputPtrRegHi);
> + CCInfo.AllocateReg(ScratchPtrRegLo);
> + CCInfo.AllocateReg(ScratchPtrRegHi);
> + MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
> + MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
> }
>
> if (Info->getShaderType() == ShaderType::COMPUTE) {
> @@ -874,7 +894,8 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
> SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
> SelectionDAG &DAG) const {
> MachineFunction &MF = DAG.getMachineFunction();
> - SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
> + const SIRegisterInfo *TRI =
> + static_cast<const SIRegisterInfo*>(MF.getSubtarget().getRegisterInfo());
>
> EVT VT = Op.getValueType();
> SDLoc DL(Op);
> @@ -882,41 +903,50 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
>
> switch (IntrinsicID) {
> case Intrinsic::r600_read_ngroups_x:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::NGROUPS_X, false);
> case Intrinsic::r600_read_ngroups_y:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::NGROUPS_Y, false);
> case Intrinsic::r600_read_ngroups_z:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::NGROUPS_Z, false);
> case Intrinsic::r600_read_global_size_x:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
> case Intrinsic::r600_read_global_size_y:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
> case Intrinsic::r600_read_global_size_z:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
> case Intrinsic::r600_read_local_size_x:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::LOCAL_SIZE_X, false);
> case Intrinsic::r600_read_local_size_y:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
> case Intrinsic::r600_read_local_size_z:
> - return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
> case Intrinsic::r600_read_tgid_x:
> return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
> - AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
> case Intrinsic::r600_read_tgid_y:
> return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
> - AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1), VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
> case Intrinsic::r600_read_tgid_z:
> return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
> - AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2), VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
> case Intrinsic::r600_read_tidig_x:
> return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
> - AMDGPU::VGPR0, VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
> case Intrinsic::r600_read_tidig_y:
> return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
> - AMDGPU::VGPR1, VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
> case Intrinsic::r600_read_tidig_z:
> return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
> - AMDGPU::VGPR2, VT);
> + TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
> case AMDGPUIntrinsic::SI_load_const: {
> SDValue Ops[] = {
> Op.getOperand(1),
> diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h
> index 07d65fb..bb9031f 100644
> --- a/lib/Target/R600/SIInstrInfo.h
> +++ b/lib/Target/R600/SIInstrInfo.h
> @@ -237,6 +237,25 @@ namespace AMDGPU {
>
> } // End namespace AMDGPU
>
> +namespace SI {
> +namespace KernelInputOffsets {
> +
> +/// Offsets in bytes from the start of the input buffer
> +enum Offsets {
> + NGROUPS_X = 0,
> + NGROUPS_Y = 4,
> + NGROUPS_Z = 8,
> + GLOBAL_SIZE_X = 12,
> + GLOBAL_SIZE_Y = 16,
> + GLOBAL_SIZE_Z = 20,
> + LOCAL_SIZE_X = 24,
> + LOCAL_SIZE_Y = 28,
> + LOCAL_SIZE_Z = 32
> +};
> +
> +} // End namespace KernelInputOffsets
> +} // End namespace SI
> +
> } // End namespace llvm
>
> namespace SIInstrFlags {
> diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
> index c28f9f4..3924e21 100644
> --- a/lib/Target/R600/SIRegisterInfo.cpp
> +++ b/lib/Target/R600/SIRegisterInfo.cpp
> @@ -324,6 +324,14 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
> return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
> case SIRegisterInfo::SCRATCH_PTR:
> return AMDGPU::SGPR2_SGPR3;
> + case SIRegisterInfo::INPUT_PTR:
> + return AMDGPU::SGPR0_SGPR1;
> + case SIRegisterInfo::TIDIG_X:
> + return AMDGPU::VGPR0;
> + case SIRegisterInfo::TIDIG_Y:
> + return AMDGPU::VGPR1;
> + case SIRegisterInfo::TIDIG_Z:
> + return AMDGPU::VGPR2;
> }
> llvm_unreachable("unexpected preloaded value type");
> }
> diff --git a/lib/Target/R600/SIRegisterInfo.h b/lib/Target/R600/SIRegisterInfo.h
> index 2439d38..29b5d0c 100644
> --- a/lib/Target/R600/SIRegisterInfo.h
> +++ b/lib/Target/R600/SIRegisterInfo.h
> @@ -89,7 +89,11 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
> TGID_Y,
> TGID_Z,
> SCRATCH_WAVE_OFFSET,
> - SCRATCH_PTR
> + SCRATCH_PTR,
> + INPUT_PTR,
> + TIDIG_X,
> + TIDIG_Y,
> + TIDIG_Z
> };
>
> /// \brief Returns the physical register that \p Value is stored in.
> --
> 1.8.5.5
>
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