[llvm] r217973 - Revert "[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors"
Robin Morisset
morisset at google.com
Wed Sep 17 11:09:14 PDT 2014
Author: morisset
Date: Wed Sep 17 13:09:13 2014
New Revision: 217973
URL: http://llvm.org/viewvc/llvm-project?rev=217973&view=rev
Log:
Revert "[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors"
It is breaking the build on the buildbots but works fine on my machine, I revert
while trying to understand what happens (it appears to depend on the compiler used
to build, I probably used a C++11 feature that is not perfectly supported by some
of the buildbots).
This reverts commit feb3176c4d006f99af8b40373abd56215a90e7cc.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=217973&r1=217972&r2=217973&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 17 13:09:13 2014
@@ -10984,33 +10984,11 @@ bool ARMTargetLowering::shouldConvertCon
bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
-Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
- ARM_MB::MemBOpt Domain) const {
+static void makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) {
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
-
- // First, if the target has no DMB, see what fallback we can use.
- if (!Subtarget->hasDataBarrier()) {
- // Some ARMv6 cpus can support data barriers with an mcr instruction.
- // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
- // here.
- if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
- Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
- ArrayRef<Value*> args = {Builder.getInt32(15), Builder.getInt32(0),
- Builder.getInt32(0), Builder.getInt32(7),
- Builder.getInt32(10), Builder.getInt32(5)};
- return Builder.CreateCall(MCR, args);
- } else {
- // Instead of using barriers, atomic accesses on these subtargets use
- // libcalls.
- llvm_unreachable("makeDMB on a target so old that it has no barriers");
- }
- } else {
- Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
- // Only a full system barrier exists in the M-class architectures.
- Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
- Constant *CDomain = Builder.getInt32(Domain);
- return Builder.CreateCall(DMB, CDomain);
- }
+ Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
+ Constant *CDomain = Builder.getInt32(Domain);
+ Builder.CreateCall(DMB, CDomain);
}
// Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=217973&r1=217972&r2=217973&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Sep 17 13:09:13 2014
@@ -393,7 +393,6 @@ namespace llvm {
Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
bool hasLoadLinkedStoreConditional() const override;
- Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
AtomicOrdering Ord) const override;
Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
Modified: llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll?rev=217973&r1=217972&r2=217973&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll Wed Sep 17 13:09:13 2014
@@ -3,8 +3,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO
; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
-; RUN: llc < %s -mtriple=armv6-apple-ios | FileCheck %s -check-prefix=ARMV6
-; RUN: llc < %s -mtriple=thumbv7m-apple-ios | FileCheck %s -check-prefix=THUMBM
define void @test1(i32* %ptr, i32 %val1) {
; ARM-LABEL: test1
@@ -17,14 +15,6 @@ define void @test1(i32* %ptr, i32 %val1)
; THUMBTWO: dmb {{ish$}}
; THUMBTWO-NEXT: str
; THUMBTWO-NEXT: dmb {{ish$}}
-; ARMV6-LABEL: test1
-; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5
-; ARMV6: str
-; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5
-; THUMBM-LABEL: test1
-; THUMBM: dmb sy
-; THUMBM: str
-; THUMBM: dmb sy
store atomic i32 %val1, i32* %ptr seq_cst, align 4
ret void
}
@@ -38,12 +28,6 @@ define i32 @test2(i32* %ptr) {
; THUMBTWO-LABEL: test2
; THUMBTWO: ldr
; THUMBTWO-NEXT: dmb {{ish$}}
-; ARMV6-LABEL: test2
-; ARMV6: ldr
-; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5
-; THUMBM-LABEL: test2
-; THUMBM: ldr
-; THUMBM: dmb sy
%val = load atomic i32* %ptr seq_cst, align 4
ret i32 %val
}
@@ -71,11 +55,6 @@ define void @test3(i8* %ptr1, i8* %ptr2)
; THUMBONE-NOT: dmb
; THUMBONE: strb
; THUMBONE-NOT: dmb
-
-; ARMV6-LABEL: test3
-; ARMV6-NOT: mcr
-; THUMBM-LABEL: test3
-; THUMBM-NOT: dmb sy
%val = load atomic i8* %ptr1 unordered, align 1
store atomic i8 %val, i8* %ptr2 unordered, align 1
ret void
@@ -85,8 +64,6 @@ define void @test4(i8* %ptr1, i8* %ptr2)
; THUMBONE-LABEL: test4
; THUMBONE: ___sync_val_compare_and_swap_1
; THUMBONE: ___sync_lock_test_and_set_1
-; ARMV6-LABEL: test4
-; THUMBM-LABEL: test4
%val = load atomic i8* %ptr1 seq_cst, align 1
store atomic i8 %val, i8* %ptr2 seq_cst, align 1
ret void
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