[PATCH] [AArch64] Refines the Cortex-A57 Machine Model

[Dave Estes]

I'm seeing strong improvements for Spec2000 on device here, so I'll try ToT too and get to the bottom of this.

Thanks.

> I tried your patch on ToT, and got the following result. (negative number is good).
> 
> spec.cpu2000.ref.175_vpr	-1.10%
> spec.cpu2000.ref.177_mesa	-2.46%
> spec.cpu2000.ref.179_art	1.96%
> spec.cpu2000.ref.183_equake	4.30%
> spec.cpu2000.ref.252_eon	2.06%
> spec.cpu2000.ref.254_gap	1.59%
> spec.cpu2000.ref.256_bzip2	1.49%
> spec.cpu2000.ref.300_twolf	3.71%

================
Comment at: lib/Target/AArch64/AArch64SchedA57.td:525
@@ +524,3 @@
+
+def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
+
----------------
Jiangning wrote:
> Where are FN?MUL[DS]rr ?
Thanks for the feedback, Jiangning.

In this case, FN?MUL[DS]rr instructions don't have a specific InstRW, because their default WriteFMul has been mapped to the correct specific SchedWrite already, A57Write_5cyc_1V. I only use InstRWs to refine instructions that aren't correct with the default mappings.

http://reviews.llvm.org/D5372