[llvm] r217839 - [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.
Juergen Ributzka
juergen at apple.com
Mon Sep 15 15:33:07 PDT 2014
Author: ributzka
Date: Mon Sep 15 17:33:06 2014
New Revision: 217839
URL: http://llvm.org/viewvc/llvm-project?rev=217839&view=rev
Log:
[FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.
Also lower sin/cos/pow to runtime lib calls.
This fixes rdar://problem/18343468.
Added:
llvm/trunk/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
Removed:
llvm/trunk/test/CodeGen/AArch64/fast-isel-frem.ll
Modified:
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=217839&r1=217838&r2=217839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Mon Sep 15 17:33:06 2014
@@ -2638,6 +2638,56 @@ bool AArch64FastISel::fastLowerIntrinsic
return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
}
+ case Intrinsic::sin:
+ case Intrinsic::cos:
+ case Intrinsic::pow: {
+ MVT RetVT;
+ if (!isTypeLegal(II->getType(), RetVT))
+ return false;
+
+ if (RetVT != MVT::f32 && RetVT != MVT::f64)
+ return false;
+
+ static const RTLIB::Libcall LibCallTable[3][2] = {
+ { RTLIB::SIN_F32, RTLIB::SIN_F64 },
+ { RTLIB::COS_F32, RTLIB::COS_F64 },
+ { RTLIB::POW_F32, RTLIB::POW_F64 }
+ };
+ RTLIB::Libcall LC;
+ bool Is64Bit = RetVT == MVT::f64;
+ switch (II->getIntrinsicID()) {
+ default:
+ llvm_unreachable("Unexpected intrinsic.");
+ case Intrinsic::sin:
+ LC = LibCallTable[0][Is64Bit];
+ break;
+ case Intrinsic::cos:
+ LC = LibCallTable[1][Is64Bit];
+ break;
+ case Intrinsic::pow:
+ LC = LibCallTable[2][Is64Bit];
+ break;
+ }
+
+ ArgListTy Args;
+ Args.reserve(II->getNumArgOperands());
+
+ // Populate the argument list.
+ for (auto &Arg : II->arg_operands()) {
+ ArgListEntry Entry;
+ Entry.Val = Arg;
+ Entry.Ty = Arg->getType();
+ Args.push_back(Entry);
+ }
+
+ CallLoweringInfo CLI;
+ CLI.setCallee(TLI.getLibcallCallingConv(LC), II->getType(),
+ TLI.getLibcallName(LC), std::move(Args));
+ if (!lowerCallTo(CLI))
+ return false;
+ updateValueMap(II, CLI.ResultReg);
+ return true;
+ }
case Intrinsic::trap: {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
.addImm(1);
Removed: llvm/trunk/test/CodeGen/AArch64/fast-isel-frem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-frem.ll?rev=217838&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-frem.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-frem.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
-
-define float @frem_f32(float %a, float %b) {
-; SMALL-LABEL: frem_f32
-; SMALL: bl _fmodf
-; LARGE-LABEL: frem_f32
-; LARGE: adrp [[REG:x[0-9]+]], _fmodf at GOTPAGE
-; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf at GOTPAGEOFF{{\]}}
-; LARGE-NEXT: blr [[REG]]
- %1 = frem float %a, %b
- ret float %1
-}
-
-define double @frem_f64(double %a, double %b) {
-; SMALL-LABEL: frem_f64
-; SMALL: bl _fmod
-; LARGE-LABEL: frem_f64
-; LARGE: adrp [[REG:x[0-9]+]], _fmod at GOTPAGE
-; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod at GOTPAGEOFF{{\]}}
-; LARGE-NEXT: blr [[REG]]
- %1 = frem double %a, %b
- ret double %1
-}
Added: llvm/trunk/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll?rev=217839&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll Mon Sep 15 17:33:06 2014
@@ -0,0 +1,96 @@
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
+
+define float @frem_f32(float %a, float %b) {
+; SMALL-LABEL: frem_f32
+; SMALL: bl _fmodf
+; LARGE-LABEL: frem_f32
+; LARGE: adrp [[REG:x[0-9]+]], _fmodf at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = frem float %a, %b
+ ret float %1
+}
+
+define double @frem_f64(double %a, double %b) {
+; SMALL-LABEL: frem_f64
+; SMALL: bl _fmod
+; LARGE-LABEL: frem_f64
+; LARGE: adrp [[REG:x[0-9]+]], _fmod at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = frem double %a, %b
+ ret double %1
+}
+
+define float @sin_f32(float %a) {
+; SMALL-LABEL: sin_f32
+; SMALL: bl _sinf
+; LARGE-LABEL: sin_f32
+; LARGE: adrp [[REG:x[0-9]+]], _sinf at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _sinf at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call float @llvm.sin.f32(float %a)
+ ret float %1
+}
+
+define double @sin_f64(double %a) {
+; SMALL-LABEL: sin_f64
+; SMALL: bl _sin
+; LARGE-LABEL: sin_f64
+; LARGE: adrp [[REG:x[0-9]+]], _sin at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _sin at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call double @llvm.sin.f64(double %a)
+ ret double %1
+}
+
+define float @cos_f32(float %a) {
+; SMALL-LABEL: cos_f32
+; SMALL: bl _cosf
+; LARGE-LABEL: cos_f32
+; LARGE: adrp [[REG:x[0-9]+]], _cosf at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _cosf at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call float @llvm.cos.f32(float %a)
+ ret float %1
+}
+
+define double @cos_f64(double %a) {
+; SMALL-LABEL: cos_f64
+; SMALL: bl _cos
+; LARGE-LABEL: cos_f64
+; LARGE: adrp [[REG:x[0-9]+]], _cos at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _cos at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call double @llvm.cos.f64(double %a)
+ ret double %1
+}
+
+define float @pow_f32(float %a, float %b) {
+; SMALL-LABEL: pow_f32
+; SMALL: bl _powf
+; LARGE-LABEL: pow_f32
+; LARGE: adrp [[REG:x[0-9]+]], _powf at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _powf at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call float @llvm.pow.f32(float %a, float %b)
+ ret float %1
+}
+
+define double @pow_f64(double %a, double %b) {
+; SMALL-LABEL: pow_f64
+; SMALL: bl _pow
+; LARGE-LABEL: pow_f64
+; LARGE: adrp [[REG:x[0-9]+]], _pow at GOTPAGE
+; LARGE: ldr [[REG]], {{\[}}[[REG]], _pow at GOTPAGEOFF{{\]}}
+; LARGE-NEXT: blr [[REG]]
+ %1 = call double @llvm.pow.f64(double %a, double %b)
+ ret double %1
+}
+declare float @llvm.sin.f32(float)
+declare double @llvm.sin.f64(double)
+declare float @llvm.cos.f32(float)
+declare double @llvm.cos.f64(double)
+declare float @llvm.pow.f32(float, float)
+declare double @llvm.pow.f64(double, double)
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