[Thumb] Don't materialize a new base register when CPSR is live

[Renato Golin]

Hi Moritz,

Why do you need to use ADDS there? Wouldn't that problem be gone if
you used a simple ADD?

Also, this comparison is redundant:

+    if (isThumb1 && !SafeToClobberCPSR)
+      return false;

could be just

+    if (!SafeToClobberCPSR)
+      return false;

though, keeping the comment is probably good.

I suppose reducing the case where you found it proved harder than usual?

cheers,
--renato

On 12 September 2014 17:44, Moritz Roth <Moritz.Roth at arm.com> wrote:
> Hi Renato,
>
>
>
> This patch is a small bugfix for the load/store optimizer. If the CPSR is
> live, we can’t safely materialize a base register + offset in Thumb-1.
>
> There is no test case because I haven’t actually seen this cause problems in
> real code – but theoretically, it’s possible to get spill code inserted
> between e.g. a CMP + Bcc, which would then be a candidate for merging.
>
>
>
> OK to commit?
>
>
>
> Cheers
>
> Moritz
>
>
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