[llvm] r217289 - [x86] Fix an embarressing bug in the INSERTPS formation code. The mask

[Chandler Carruth]

Author: chandlerc
Date: Fri Sep  5 18:19:45 2014
New Revision: 217289

URL: http://llvm.org/viewvc/llvm-project?rev=217289&view=rev
Log:
[x86] Fix an embarressing bug in the INSERTPS formation code. The mask
computation was totally wrong, but somehow it didn't really show up with
llc.

I've added an assert that triggers on multiple existing test cases and
updated one of them to show the correct value.

There appear to still be more bugs lurking around insertps's mask. =/
However, note that this only really impacts the new vector shuffle
lowering.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/vec_set-3.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=217289&r1=217288&r2=217289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  5 18:19:45 2014
@@ -7417,11 +7417,12 @@ static SDValue lowerV4F32VectorShuffle(S
         if ((ZMask | 1 << V2Index) == 0xF)
           V1 = DAG.getUNDEF(MVT::v4f32);
 
+        unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
+        assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
+
         // Insert the V2 element into the desired position.
-        SDValue InsertPSMask =
-            DAG.getIntPtrConstant(Mask[V2Index] << 6 | V2Index << 4 | ZMask);
         return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
-                           InsertPSMask);
+                           DAG.getConstant(InsertPSMask, MVT::i8));
       }
     }
 

Modified: llvm/trunk/test/CodeGen/X86/vec_set-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-3.ll?rev=217289&r1=217288&r2=217289&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-3.ll Fri Sep  5 18:19:45 2014
@@ -8,7 +8,7 @@ define <4 x float> @test(float %a) {
 ; CHECK-NEXT:    retl
 ;
 ; CHECK-EXP-LABEL: test:
-; CHECK-EXP:         insertps $285, {{.*}}, %xmm0
+; CHECK-EXP:         insertps $29, {{.*}}, %xmm0
 ; CHECK-EXP-NEXT:    retl
 
 entry: