[PATCH] R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()

[Matt Arsenault]

On Sep 3, 2014, at 5:38 PM, Tom Stellard <thomas.stellard at amd.com> wrote:

> We must constrain the destination register class of legalized operands
> to a VGPR class or else the illegal operand may be folded back into
> the instruction by the register coalescer.
> 
> This fixes a bug in add.ll that will be uncovered by future commits.
> ---
> lib/Target/R600/SIInstrInfo.cpp | 5 +++++
> 1 file changed, 5 insertions(+)
> 
> diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> index 6595db8..2833a4d 100644
> --- a/lib/Target/R600/SIInstrInfo.cpp
> +++ b/lib/Target/R600/SIInstrInfo.cpp
> @@ -988,6 +988,11 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
>   }
> 
>   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
> +  if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
> +    VRC = &AMDGPU::VReg_64RegClass;
> +  } else {
> +    VRC = &AMDGPU::VReg_32RegClass;
> +  }
>   unsigned Reg = MRI.createVirtualRegister(VRC);
>   BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
>           Reg).addOperand(MO);
> -- 
> 1.8.5.5
> 
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Is this a better fix for the same problem I fixed in the mul SALU patch?