[PATCH] [InstCombine] Attempt to eliminate redundant loads whose addresses are dependent on the result of a select instruction.

[Tilmann Scheller]

Hi,

attached is the following patch:

[PATCH] [InstCombine] Attempt to eliminate redundant loads whose addresses are dependent on the result of a select instruction.

If both values have already been loaded into registers the load becomes redundant and can be replaced with a select on the two values instead, e.g. we can do the following transformation:

a = (load (gep idx_a))
b = (load (gep idx_b))
c = (load (gep (select (cond, idx_a, idx_b))))
  -->
a = (load (gep idx_a))
b = (load (gep idx_b))
c = (select (cond, a, b))



This particular pattern occurs in the hottest loop of 175.vpr from SPEC CPU2000. Haven't done any measurements yet but I would assume it improves performance (GCC is doing the above optimization and is ~10% faster on ARM)

This is my first patch for InstCombine, feedback welcome :)

Regards,

Tilmann
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