[llvm] r216971 - R600/SI: Relax some ordering in tests.

[Matt Arsenault]

Author: arsenm
Date: Tue Sep  2 16:45:50 2014
New Revision: 216971

URL: http://llvm.org/viewvc/llvm-project?rev=216971&view=rev
Log:
R600/SI: Relax some ordering in tests.

This will help with enabling misched

Modified:
    llvm/trunk/test/CodeGen/R600/rotl.i64.ll
    llvm/trunk/test/CodeGen/R600/rotl.ll
    llvm/trunk/test/CodeGen/R600/rotr.i64.ll
    llvm/trunk/test/CodeGen/R600/sext-in-reg.ll

Modified: llvm/trunk/test/CodeGen/R600/rotl.i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/rotl.i64.ll?rev=216971&r1=216970&r2=216971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/rotl.i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/rotl.i64.ll Tue Sep  2 16:45:50 2014
@@ -1,10 +1,11 @@
 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @s_rotl_i64:
-; SI: S_SUB_I32
-; SI: S_LSHR_B64
-; SI: S_LSHL_B64
+; SI-DAG: S_LSHL_B64
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_LSHR_B64
 ; SI: S_OR_B64
+; SI: S_ENDPGM
 define void @s_rotl_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
 entry:
   %0 = shl i64 %x, %y
@@ -16,11 +17,12 @@ entry:
 }
 
 ; FUNC-LABEL: @v_rotl_i64:
-; SI: V_LSHL_B64
-; SI: V_SUB_I32
+; SI-DAG: V_LSHL_B64
+; SI-DAG: V_SUB_I32
 ; SI: V_LSHR_B64
 ; SI: V_OR_B32
 ; SI: V_OR_B32
+; SI: S_ENDPGM
 define void @v_rotl_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
 entry:
   %x = load i64 addrspace(1)* %xptr, align 8

Modified: llvm/trunk/test/CodeGen/R600/rotl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/rotl.ll?rev=216971&r1=216970&r2=216971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/rotl.ll (original)
+++ llvm/trunk/test/CodeGen/R600/rotl.ll Tue Sep  2 16:45:50 2014
@@ -20,10 +20,11 @@ entry:
 }
 
 ; FUNC-LABEL: @rotl_v2i32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: V_ALIGNBIT_B32
+; SI: S_ENDPGM
 define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
 entry:
   %0 = shl <2 x i32> %x, %y
@@ -35,14 +36,15 @@ entry:
 }
 
 ; FUNC-LABEL: @rotl_v4i32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI: S_ENDPGM
 define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
 entry:
   %0 = shl <4 x i32> %x, %y

Modified: llvm/trunk/test/CodeGen/R600/rotr.i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/rotr.i64.ll?rev=216971&r1=216970&r2=216971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/rotr.i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/rotr.i64.ll Tue Sep  2 16:45:50 2014
@@ -1,8 +1,8 @@
 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @s_rotr_i64
-; SI: S_LSHR_B64
-; SI: S_SUB_I32
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_LSHR_B64
 ; SI: S_LSHL_B64
 ; SI: S_OR_B64
 define void @s_rotr_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
@@ -16,9 +16,9 @@ entry:
 }
 
 ; FUNC-LABEL: @v_rotr_i64
-; SI: V_LSHR_B64
-; SI: V_SUB_I32
-; SI: V_LSHL_B64
+; SI-DAG: V_SUB_I32
+; SI-DAG: V_LSHR_B64
+; SI-DAG: V_LSHL_B64
 ; SI: V_OR_B32
 ; SI: V_OR_B32
 define void @v_rotr_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {

Modified: llvm/trunk/test/CodeGen/R600/sext-in-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sext-in-reg.ll?rev=216971&r1=216970&r2=216971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/sext-in-reg.ll (original)
+++ llvm/trunk/test/CodeGen/R600/sext-in-reg.ll Tue Sep  2 16:45:50 2014
@@ -195,10 +195,11 @@ define void @sext_in_reg_i1_in_i32_other
 }
 
 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
-; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
-; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
-; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
-; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
+; SI-DAG: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
+; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
+; SI-DAG: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
+; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
+; SI: S_ENDPGM
 
 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
 ; EG-NOT: BFE