[llvm] r216908 - Enable splitting indexing from loads with TargetConstants
Hal Finkel
hfinkel at anl.gov
Tue Sep 2 09:05:24 PDT 2014
Author: hfinkel
Date: Tue Sep 2 11:05:23 2014
New Revision: 216908
URL: http://llvm.org/viewvc/llvm-project?rev=216908&view=rev
Log:
Enable splitting indexing from loads with TargetConstants
When I recommitted r208640 (in r216898) I added an exclusion for TargetConstant
offsets, as there is no guarantee that a backend can handle them on generic
ADDs (even if it generates them during address-mode matching) -- and,
specifically, applying this transformation directly with TargetConstants caused
a self-hosting failure on PPC64. Ignoring all TargetConstants, however, is less
than ideal. Instead, for non-opaque constants, we can convert them into regular
constants for use with the generated ADD (or SUB).
Added:
llvm/trunk/test/CodeGen/PowerPC/split-index-tc.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=216908&r1=216907&r2=216908&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 2 11:05:23 2014
@@ -8029,8 +8029,19 @@ SDValue DAGCombiner::SplitIndexingFromLo
assert(AM != ISD::UNINDEXED);
SDValue BP = LD->getOperand(1);
SDValue Inc = LD->getOperand(2);
- assert(Inc.getOpcode() != ISD::TargetConstant &&
- "Cannot split out indexing using target constants");
+
+ // Some backends use TargetConstants for load offsets, but don't expect
+ // TargetConstants in general ADD nodes. We can convert these constants into
+ // regular Constants (if the constant is not opaque).
+ assert((Inc.getOpcode() != ISD::TargetConstant ||
+ !cast<ConstantSDNode>(Inc)->isOpaque()) &&
+ "Cannot split out indexing using opaque target constants");
+ if (Inc.getOpcode() == ISD::TargetConstant) {
+ ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
+ Inc = DAG.getConstant(*ConstInc->getConstantIntValue(),
+ ConstInc->getValueType(0));
+ }
+
unsigned Opc =
(AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
@@ -8071,16 +8082,18 @@ SDValue DAGCombiner::visitLOAD(SDNode *N
// Indexed loads.
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
- // If this load has an TargetConstant offset, then we cannot split the
- // indexing into an add/sub directly (that TargetConstant may not be
- // valid for a different type of node).
- bool HasTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant;
+ // If this load has an opaque TargetConstant offset, then we cannot split
+ // the indexing into an add/sub directly (that TargetConstant may not be
+ // valid for a different type of node, and we cannot convert an opaque
+ // target constant into a regular constant).
+ bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
+ cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
if (!N->hasAnyUseOfValue(0) &&
- ((MaySplitLoadIndex && !HasTCInc) || !N->hasAnyUseOfValue(1))) {
+ ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
SDValue Index;
- if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasTCInc) {
+ if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
Index = SplitIndexingFromLoad(LD);
// Try to fold the base pointer arithmetic into subsequent loads and
// stores.
Added: llvm/trunk/test/CodeGen/PowerPC/split-index-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/split-index-tc.ll?rev=216908&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/split-index-tc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/split-index-tc.ll Tue Sep 2 11:05:23 2014
@@ -0,0 +1,82 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%"class.llvm::MachineOperand" = type { i8, [3 x i8], i64, i64*, i64 }
+
+; Function Attrs: nounwind
+define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align 2 {
+
+; If we were able to split out the indexing, the load with update should be
+; removed (resulting in a nearly-empty output).
+; CHECK-LABEL: @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj
+; CHECK-NOT: lhzu
+
+entry:
+ %0 = load %"class.llvm::MachineOperand"** undef, align 8
+ br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
+
+cond.false.i123: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
+ unreachable
+
+_ZNK4llvm14MachineOperand6getRegEv.exit: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
+ %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand"* %0, i64 undef, i32 1
+ %1 = bitcast [3 x i8]* %IsDef.i to i24*
+ %bf.load.i = load i24* %1, align 1
+ %2 = and i24 %bf.load.i, 128
+ br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph
+
+for.body.lr.ph: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
+ %3 = zext i24 %2 to i32
+ br i1 undef, label %cond.false.i134, label %_ZNK4llvm18MCRegAliasIteratordeEv.exit
+
+for.cond.cleanup: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
+ br i1 undef, label %_ZNK4llvm14MachineOperand5isDefEv.exit, label %cond.false.i129
+
+cond.false.i129: ; preds = %for.cond.cleanup
+ unreachable
+
+_ZNK4llvm14MachineOperand5isDefEv.exit: ; preds = %for.cond.cleanup
+ br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit247, label %cond.false.i244
+
+cond.false.i134: ; preds = %for.body.lr.ph
+ unreachable
+
+_ZNK4llvm18MCRegAliasIteratordeEv.exit: ; preds = %for.body.lr.ph
+ unreachable
+
+cond.false.i244: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
+ unreachable
+
+_ZNK4llvm14MachineOperand6getRegEv.exit247: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
+ br i1 undef, label %if.then53, label %if.end55
+
+if.then53: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
+ unreachable
+
+if.end55: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
+ br i1 undef, label %_ZNK4llvm14MachineOperand6isDeadEv.exit262, label %cond.false.i257
+
+cond.false.i257: ; preds = %if.end55
+ unreachable
+
+_ZNK4llvm14MachineOperand6isDeadEv.exit262: ; preds = %if.end55
+ %bf.load.i259 = load i24* %1, align 1
+ br i1 undef, label %if.then57, label %if.else59
+
+if.then57: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
+ unreachable
+
+if.else59: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
+ br i1 undef, label %if.end89, label %if.then62
+
+if.then62: ; preds = %if.else59
+ unreachable
+
+if.end89: ; preds = %if.else59
+ unreachable
+}
+
+attributes #0 = { nounwind }
+
+
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