[llvm] r216734 - AArch64: only try to get operand of a known node.

[Tim Northover]

Author: tnorthover
Date: Fri Aug 29 10:34:58 2014
New Revision: 216734

URL: http://llvm.org/viewvc/llvm-project?rev=216734&view=rev
Log:
AArch64: only try to get operand of a known node.

A bug in r216725 meant we tried to discover the type of a SETCC before
confirming the node actually was a SETCC.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/cond-sel.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=216734&r1=216733&r2=216734&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Aug 29 10:34:58 2014
@@ -7994,18 +7994,18 @@ static SDValue performVSelectCombine(SDN
 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   EVT ResVT = N->getValueType(0);
-  EVT SrcVT = N0.getOperand(0).getValueType();
-  int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
+
+  if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
+    return SDValue();
 
   // If NumMaskElts == 0, the comparison is larger than select result. The
   // largest real NEON comparison is 64-bits per lane, which means the result is
   // at most 32-bits and an illegal vector. Just bail out for now.
+  EVT SrcVT = N0.getOperand(0).getValueType();
+  int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
   if (!ResVT.isVector() || NumMaskElts == 0)
     return SDValue();
 
-  if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
-    return SDValue();
-
   SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
   EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
 

Modified: llvm/trunk/test/CodeGen/AArch64/cond-sel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cond-sel.ll?rev=216734&r1=216733&r2=216734&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/cond-sel.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/cond-sel.ll Fri Aug 29 10:34:58 2014
@@ -224,3 +224,10 @@ define <1 x i1> @test_wide_comparison(i3
   %res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer
   ret <1 x i1> %res
 }
+
+define i32 @test_select_undef() {
+; CHECK-LABEL: test_select_undef:
+; CHECK: ret
+  %res = select i1 undef, i32 0, i32 42
+  ret i32 %res
+}