[PATCH] [AArch64] Fix an ISEL failure around half float data type

[Jiangning Liu]

Hi t.p.northover,

This patch is to fix an ISEL failure around half float data type. The fix covers two things,

1) Some bitcast patterns around v8f16 are missing in AArch64 back-end.
2) The promotion of v8f16 to v8i16 for the operand of load/store is missing. Since for little-end we only generate ldr/str, we can use big-endian to capture the failure exposed by pattern match for instruction ld1/st1.

Thanks,
-Jiangning

http://reviews.llvm.org/D5094

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/aarch64_f16_be.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D5094.13023.patch
Type: text/x-patch
Size: 4768 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140828/848fa970/attachment.bin>