[llvm] r216538 - [x86] Fix a regression introduced with r213897 for 32-bit targets where

[Chandler Carruth]

Author: chandlerc
Date: Wed Aug 27 06:39:47 2014
New Revision: 216538

URL: http://llvm.org/viewvc/llvm-project?rev=216538&view=rev
Log:
[x86] Fix a regression introduced with r213897 for 32-bit targets where
we stopped efficiently lowering sextload using the SSE41 instructions
for that operation.

This is a consequence of a bad predicate I used thinking of the memory
access needs. The code actually handles the cases where the predicate
doesn't apply, and handles them much better. =] Simple fix and a test
case added. Fixes PR20767.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/vec_sext.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=216538&r1=216537&r2=216538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 27 06:39:47 2014
@@ -1016,10 +1016,8 @@ void X86TargetLowering::resetOperationAc
     // scalars) and extend in-register to a legal 128-bit vector type. For sext
     // loads these must work with a single scalar load.
     setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
-    if (Subtarget->is64Bit()) {
-      setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
-      setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
-    }
+    setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
+    setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
     setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
     setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
     setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);

Modified: llvm/trunk/test/CodeGen/X86/vec_sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_sext.ll?rev=216538&r1=216537&r2=216538&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_sext.ll Wed Aug 27 06:39:47 2014
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86-64
-; PR 9267
+; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
 
 define<4 x i32> @func_16_32() {
   %F = load <4 x i16>* undef
@@ -67,3 +67,14 @@ define<4 x i64> @const_16_64() {
   ret <4 x i64> %G
 }
 
+define <4 x i32> @sextload(<4 x i16>* %ptr) {
+; From PR20767 - make sure that we correctly use SSE4.1 to do sign extension
+; loads for both 32-bit and 64-bit x86 targets.
+; CHECK-LABEL: sextload:
+; CHECK:         vpmovsxwd {{.*}}, %xmm0
+; CHECK-NEXT:    ret
+entry:
+  %l = load<4 x i16>* %ptr
+  %m = sext<4 x i16> %l to <4 x i32>
+  ret <4 x i32> %m
+}