[AMDGPU][PATCH 0/3] barriers/memory-fences related additions
Hilloulin Damien
damien.hilloulin at supelec.fr
Thu Aug 21 17:33:33 PDT 2014
Hello LLVM developers,
This serie of patches aims at defining the new intrinsics necessary to
my libclc
serie of patches to implement barries/memory fences on AMDGPUs.
This patch serie only provides stubs implementations of the necessary
intrinsics.
For example, on evergreen hardware, we would need to modify the read/writes
surrounding operations (placed before or in the same loop) so that they make
an ACK when completed.
On Evergreen and SI, everything is lowered to a barrier instruction in
fact (for
now).
I plan to add the necessary transformations in a following serie of patches.
(It's my first patches to an open-source project, so don't hesitate to
point me my
mistakes/errors/indentation problems etc :) ).
Sincerely,
Damien Hilloulin.
[1/3] Addition of the new intrinsics in AMDGPUIntrinsics.td
This patch adds the definitions of the intrisics used for
barriers/memory fences support.
[2/3] Stubs implementation of the new intrinsics on Evergreen
This patch adds some stubs to provide a first implementation of the
intrinsics for barriers and memory fences. The barrier.nofence()
intrinsic is the only intrinsic correctly implemented (for sure)
with this patch. Maybe the barrier.local() intrinsic can be
considered ok like this as the LDS memory is atomic. The other
intrinsics need to use WAIT_ACK in some way and that we modify
the surroundings memory operations with ACK.
[3/3] Stubs implementation of the new intrinsics on Southern_Islands
This patch is a first implementation of the newly added intrinsics for
barriers/memory fences on SI. It may need additional
modifications just like the Evergreen intrinsics though.
lib/Target/R600/AMDGPUIntrinsics.td | 11 +++++
lib/Target/R600/EvergreenInstructions.td | 69
+++++++++++++++++++++++++++++++-
lib/Target/R600/SIInstructions.td | 16 +++++++-
3 files changed, 94 insertions(+), 2 deletions(-)
--
1.9.1
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