[PATCH] ARM: Enable DP copy, load and store instructions for FPv4-SP

[Oliver Stannard]

================
Comment at: lib/Target/ARM/ARMCallingConv.h:182
@@ -180,3 +181,3 @@
   // AAPCS HFAs must have 1-4 elements, all of the same type
-  assert(PendingHAMembers.size() < 8);
+  assert(PendingHAMembers.size() < 4);
   if (PendingHAMembers.size() > 0)
----------------
Renato Golin wrote:
> Isn't this an independent fix?
This is part of the revert of http://reviews.llvm.org/rL209650. r209650 used this mechanism to pass a double as 2 i32s, meaning that an HFA of 4 doubles would have 8 members. Doubles will now show up here as f64s, so the assertion can be tightened up again.

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:3268
@@ -3235,2 +3267,3 @@
                              SDLoc dl) const {
+  assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
   SDValue Cmp;
----------------
Renato Golin wrote:
> Is this the only such assert, or just the one that you hit during tests?
The only other legal floating-point type for FPv4-SP is f32, which can be handled by this function. Vector types are only legal for NEON.

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:3492
@@ +3491,3 @@
+                                   SDValue Cmp, SelectionDAG &DAG) const {
+  if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
+    FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
----------------
Renato Golin wrote:
> Would this ever be called by v2f64 types?
No, because v2f64 is not a legal type when isFPOnlySP, and this is only called while legalizing operations, which happens after legalizing types.

http://reviews.llvm.org/D4907