[llvm] r216136 - [PeepholeOptimizer] Take advantage of the isExtractSubreg property in the

[Quentin Colombet]

Author: qcolombet
Date: Wed Aug 20 18:13:02 2014
New Revision: 216136

URL: http://llvm.org/viewvc/llvm-project?rev=216136&view=rev
Log:
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.

This patch is a step toward transforming:
udiv	r0, r0, r2
udiv	r1, r1, r3
vmov.32	d16[0], r0
vmov.32	d16[1], r1
vmov	r0, r1, d16
bx	lr

into:
udiv	r0, r0, r2
udiv	r1, r1, r3
bx	lr

Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1

Comming patches will fix that and update the related test case.

<rdar://problem/12702965>

Modified:
    llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp

Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=216136&r1=216135&r2=216136&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Wed Aug 20 18:13:02 2014
@@ -162,7 +162,8 @@ namespace {
     /// not recognized by the register coalescer.
     bool isUncoalescableCopy(const MachineInstr &MI) {
       return MI.isBitcast() || (!DisableAdvCopyOpt &&
-                                MI.isRegSequenceLike());
+                                (MI.isRegSequenceLike() ||
+                                 MI.isExtractSubregLike()));
     }
   };
 
@@ -1346,28 +1347,10 @@ bool ValueTracker::getNextSourceFromInse
   return true;
 }
 
-/// Extract the inputs from EXTRACT_SUBREG.
-/// EXTRACT_SUBREG vreg1:sub1, sub0, would produce:
-/// - vreg1:sub1, sub0
-static void
-getExtractSubregInputs(const MachineInstr &MI,
-                       TargetInstrInfo::RegSubRegPairAndIdx &InputReg) {
-  assert(MI.isExtractSubreg() && "Instruction do not have the proper type");
-  // We are looking at:
-  // Def = EXTRACT_SUBREG v0.sub1, sub0.
-  const MachineOperand &MOReg = MI.getOperand(1);
-  const MachineOperand &MOSubIdx = MI.getOperand(2);
-  assert(MOSubIdx.isImm() &&
-         "The subindex of the extract_subreg is not an immediate");
-
-  InputReg.Reg = MOReg.getReg();
-  InputReg.SubReg = MOReg.getSubReg();
-  InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
-}
-
 bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
                                                   unsigned &SrcSubReg) {
-  assert(Def->isExtractSubreg() && "Invalid definition");
+  assert((Def->isExtractSubreg() ||
+          Def->isExtractSubregLike()) && "Invalid definition");
   // We are looking at:
   // Def = EXTRACT_SUBREG v0, sub0
 
@@ -1376,9 +1359,14 @@ bool ValueTracker::getNextSourceFromExtr
   if (DefSubReg)
     return false;
 
+  if (!TII)
+    // We could handle the EXTRACT_SUBREG here, but we do not want to
+    // duplicate the code from the generic TII.
+    return false;
+
   TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
-  assert(DefIdx == 0 && "Invalid definition");
-  getExtractSubregInputs(*Def, ExtractSubregInputReg);
+  if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
+    return false;
 
   // Bails if we have to compose sub registers.
   // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
@@ -1430,7 +1418,7 @@ bool ValueTracker::getNextSourceImpl(uns
     return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
   if (Def->isInsertSubreg())
     return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
-  if (Def->isExtractSubreg())
+  if (Def->isExtractSubreg() || Def->isExtractSubregLike())
     return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
   if (Def->isSubregToReg())
     return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);