[PATCH] Teach the AArch64 backend about v4f16 and v8f16

[Oliver Stannard]

* Added ABI tests
* Added tests for NEON loads/stores (and added a few missing patterns)
* Added tests for bitcasts
* Tightened up tests which do not specify registers (ignoring some of the larger v8f16 outputs, as they use many vector inserts/extracts and re-use registers which I could not work out a good way to test)
* Fixed out of date comment

http://reviews.llvm.org/D4955

Files:
  include/llvm/CodeGen/MachineValueType.h
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/Target/AArch64/AArch64CallingConvention.td
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  test/CodeGen/AArch64/arm64-aapcs.ll
  test/CodeGen/AArch64/fp16-instructions.ll
  test/CodeGen/AArch64/fp16-v4-instructions.ll
  test/CodeGen/AArch64/fp16-v8-instructions.ll
  test/CodeGen/AArch64/fp16-vector-bitcast.ll
  test/CodeGen/AArch64/fp16-vector-load-store.ll
  test/CodeGen/AArch64/fp16-vector-shuffle.ll
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