[llvm] r216064 - ARM: Fix codegen for rbit intrinsic

[Yi Kong]

Author: kongyi
Date: Wed Aug 20 05:40:20 2014
New Revision: 216064

URL: http://llvm.org/viewvc/llvm-project?rev=216064&view=rev
Log:
ARM: Fix codegen for rbit intrinsic

LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.

The bug was originally introduced in r211057.

Differential Revision: http://reviews.llvm.org/D4980

Added:
    llvm/trunk/test/CodeGen/AArch64/rbit.ll
    llvm/trunk/test/CodeGen/ARM/rbit.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=216064&r1=216063&r2=216064&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 20 05:40:20 2014
@@ -2642,9 +2642,9 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHA
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::arm_rbit: {
-    assert(Op.getOperand(0).getValueType() == MVT::i32 &&
+    assert(Op.getOperand(1).getValueType() == MVT::i32 &&
            "RBIT intrinsic must have i32 type!");
-    return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(0));
+    return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
   }
   case Intrinsic::arm_thread_pointer: {
     EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

Added: llvm/trunk/test/CodeGen/AArch64/rbit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/rbit.ll?rev=216064&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/rbit.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/rbit.ll Wed Aug 20 05:40:20 2014
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: rbit32
+; CHECK: rbit w0, w0
+define i32 @rbit32(i32 %t) {
+entry:
+  %rbit.i = call i32 @llvm.aarch64.rbit.i32(i32 %t)
+  ret i32 %rbit.i
+}
+
+; CHECK-LABEL: rbit64
+; CHECK: rbit x0, x0
+define i64 @rbit64(i64 %t) {
+entry:
+  %rbit.i = call i64 @llvm.aarch64.rbit.i64(i64 %t)
+  ret i64 %rbit.i
+}
+
+declare i64 @llvm.aarch64.rbit.i64(i64)
+declare i32 @llvm.aarch64.rbit.i32(i32)

Added: llvm/trunk/test/CodeGen/ARM/rbit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/rbit.ll?rev=216064&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/rbit.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/rbit.ll Wed Aug 20 05:40:20 2014
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=armv8-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: rbit
+; CHECK: rbit r0, r0
+define i32 @rbit(i32 %t) {
+entry:
+  %rbit = call i32 @llvm.arm.rbit(i32 %t)
+  ret i32 %rbit
+}
+
+; CHECK-LABEL: rbit_constant
+; CHECK: mov r0, #0
+; CHECK: rbit r0, r0
+define i32 @rbit_constant() {
+entry:
+  %rbit.i = call i32 @llvm.arm.rbit(i32 0)
+  ret i32 %rbit.i
+}
+
+declare i32 @llvm.arm.rbit(i32)