[PATCH] [AArch64] Generate CMN when comparing a short int with minus

[Tim Northover]

Hi David,

This looks fine mostly; just a couple of minor nits.

Cheers.

Tim.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1084-1087
@@ -1081,4 +1083,6 @@
   }
-
-  SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
-  AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
+  // Because the imm operand of ADDS is an unsigned immediate, in the range 0 to
+  // 4095.For i8 operand, the largest immediate is 255, it can be handled well.
+  // For i16 operand, the largest immediate is larger than 4095, it should be
+  // optimized here.
+  // eg:movz w1, #65535; ldrh w0, [x0, #0]; cmp w0, w1
----------------
I think you should probably mention the fundamental property you're relying on here: that (zext LHS) == (zext RHS) if and only if (sext LHS) == (sext RHS).

Your checks are all aimed at determining
  - whether LHS and RHS really are zexted
  - whether making the transformation would be profitable.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1096
@@ +1095,3 @@
+        LHS.getNode()->hasNUsesOfValue(1, 0)) {
+      short int ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
+      if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
----------------
int16_t would be better here.

http://reviews.llvm.org/D4966