[PATCH] Implement emitLeading/TrailingFence in the ARM backend

[Robin Morisset]

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Comment at: lib/Target/ARM/ARMISelLowering.cpp:10883
@@ +10882,3 @@
+        return; // Nothing to do
+      MakeDMB(Builder, ARM_MB::ISH);
+      return;
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I just found that the test CodeGen/ARM/swift-atomics suggest that this case should fall-through (i.e. that a DMB ishst is correct in this case for Swift processor). I can change it, but I would love to link to some documentation saying so more clearly first, and I cannot seem to find it. Does anyone know where this is documented (or at least can confirm that dmb ishst is a valid leading fence for seq_cst stores)?

http://reviews.llvm.org/D4960