[llvm] r215922 - [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Quentin Colombet
qcolombet at apple.com
Mon Aug 18 10:55:56 PDT 2014
Author: qcolombet
Date: Mon Aug 18 12:55:56 2014
New Revision: 215922
URL: http://llvm.org/viewvc/llvm-project?rev=215922&view=rev
Log:
[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Logic instructions.
<rdar://problem/15607571>
Modified:
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=215922&r1=215921&r2=215922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Aug 18 12:55:56 2014
@@ -2097,4 +2097,13 @@ def WriteRSQRTPSYm : SchedWriteRes<[HWPo
}
def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>;
+//-- Logic instructions --//
+
+// AND, ANDN, OR, XOR PS/PD.
+// x,x / v,v,v.
+def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
+// x,m / v,v,m.
+def : InstRW<[WriteP5Ld, ReadAfterLd],
+ (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
+
} // SchedModel
More information about the llvm-commits
mailing list