[PATCH] Teach the AArch64 backend about v4f16 and v8f16

[Oliver Stannard]

Hi t.p.northover,

This is the vector counterpart to D4879, and teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations.

http://reviews.llvm.org/D4955

Files:
  include/llvm/CodeGen/MachineValueType.h
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/Target/AArch64/AArch64CallingConvention.td
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  test/CodeGen/AArch64/fp16-v4-instructions.ll
  test/CodeGen/AArch64/fp16-v8-instructions.ll
  test/CodeGen/AArch64/fp16-vector-shuffle.ll
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