PATCH: R600/SI: LDS improvements
Matt Arsenault
Matthew.Arsenault at amd.com
Fri Aug 15 13:35:13 PDT 2014
On 08/15/2014 12:49 PM, Tom Stellard wrote:
> Hi,
>
> The attached patches improve instruction selection for LDS instructions.
> The highlights include using a ComplexPattern for LDS instructions to do a
> better job at folding immediate offsets into the instruction and also
> selecting the read2 and write2 instructions for 64-bit loads/stores with
> 32-bit alignment.
>
> -Tom
>
> 0001-R600-SI-Use-correct-helper-class-for-DS_WRITE2-instr.patch
>
>
> From 8aded2edc5cd2cd3750cb1422e790ce7105143dd Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 15 Aug 2014 11:09:50 -0400
> Subject: [PATCH 1/4] R600/SI: Use correct helper class for DS_WRITE2
> instructions
>
> DS_1A uses a single offset encoding, so offset1 wasn't being
> encoded.
> ---
> lib/Target/R600/SIInstrInfo.td | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 3c5a3a2..7560cef 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -842,7 +842,7 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
> let vdst = 0;
> }
>
> -class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
> +class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
> op,
> (outs),
> (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
> -- 1.8.1.5
>
LGTM
> 0002-R600-SI-Wrap-local-memory-pointer-in-AssertZExt-on-S.patch
>
>
> From 469739966c154cc88231d99e5ae32dbf1ffb93c0 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 14 Aug 2014 13:41:46 -0400
> Subject: [PATCH 2/4] R600/SI: Wrap local memory pointer in AssertZExt on SI
>
> These pointers are really just offsets and they will always be
> less than 16-bits. Using AssertZExt allows us to use computeKnownBits
> to prove that these values are positive. We will use this information
> in a later commit.
> ---
> lib/Target/R600/SIISelLowering.cpp | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index c757b05..880dfc0 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -446,6 +446,18 @@ SDValue SITargetLowering::LowerFormalArguments(
> SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
> 36 + VA.getLocMemOffset(),
> Ins[i].Flags.isSExt());
> +
> + const Type *ParamTy = FType->getParamType(Ins[i].OrigArgIndex);
> + if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
> + ParamTy->isPointerTy() &&
> + ParamTy->getPointerAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
This would probably be nicer by dyn_casting to PointerType and
getAddressSpace
> + // On SI local pointers are just offsets into LDS, so they are always
> + // less than 16-bits. On CI and newer they could potentially be
> + // real pointers, so we can't guarantee their size.
> + Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
> + DAG.getValueType(MVT::i16));
> + }
> +
> InVals.push_back(Arg);
> continue;
> }
> -- 1.8.1.5
>
> 0003-R600-SI-Use-a-ComplexPattern-for-DS-loads-and-stores.patch
>
>
> From 51816df1736486e8a06d6d13c97f5c81a2ce1971 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 14 Aug 2014 13:46:07 -0400
> Subject: [PATCH 3/4] R600/SI: Use a ComplexPattern for DS loads and stores
>
> ---
> lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 41 ++++++++
> lib/Target/R600/SIInstrInfo.td | 2 +
> lib/Target/R600/SIInstructions.td | 50 ++++------
> test/CodeGen/R600/32-bit-local-address-space.ll | 27 ++---
> test/CodeGen/R600/gep-address-space.ll | 8 +-
> test/CodeGen/R600/local-64.ll | 126 ++++++++++++------------
> test/CodeGen/R600/local-memory-two-objects.ll | 9 +-
> 7 files changed, 152 insertions(+), 111 deletions(-)
>
> diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> index 349b8d2..5933919 100644
> --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> @@ -88,6 +88,9 @@ private:
> SDValue& Offset);
> bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
> bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
> + bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
> + unsigned OffsetBits) const;
> + bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
> void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
> SDValue &SOffset, SDValue &Offset, SDValue &Offen,
> SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
> @@ -744,6 +747,44 @@ SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
> return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
> }
>
> +bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
> + unsigned OffsetBits) const {
> + const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
> + if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
> + (OffsetBits == 8 && !isUInt<8>(Offset)))
> + return false;
> +
> + if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
> + return true;
> +
> + // On Southern Islands instruction with a negative base value and an offset
> + // don't seem to work.
> + APInt KnownZero;
> + APInt KnownOne;
> + CurDAG->computeKnownBits(Base, KnownZero, KnownOne);
> + return KnownZero.countLeadingOnes() > 0;
You can use SelectionDAG::SignBitIsZero for this
> +}
> +
> +bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
> + SDValue &Offset) const {
> + if (CurDAG->isBaseWithConstantOffset(Addr)) {
> + SDValue N0 = Addr.getOperand(0);
> + SDValue N1 = Addr.getOperand(1);
> + ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
> + if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
> + // (add n0, c0)
> + Base = N0;
> + Offset = N1;
> + return true;
> + }
> + }
> +
> + // default case
> + Base = Addr;
> + Offset = CurDAG->getTargetConstant(0, MVT::i16);
> + return true;
> +}
> +
> static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
> return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
> Ptr), 0);
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 7560cef..5357af9 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -191,6 +191,8 @@ def tfe : Operand <i1> {
> // Complex patterns
> //===----------------------------------------------------------------------===//
>
> +def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
> +
> def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
> def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
> def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 60611df..9181f24 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -2514,41 +2514,27 @@ def : ROTRPattern <V_ALIGNBIT_B32>;
> /********** Load/Store Patterns **********/
> /********** ======================= **********/
>
> -multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
> - def : Pat <
> - (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
> - (inst (i1 0), $ptr, (as_i16imm $offset))
> - >;
> -
> - def : Pat <
> - (frag i32:$src0),
> - (vt (inst 0, $src0, 0))
> - >;
> -}
> -
> -defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
> -defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
> -defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
> -defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
> -defm : DSReadPat <DS_READ_B32, i32, local_load>;
> -defm : DSReadPat <DS_READ_B64, v2i32, local_load>;
> +class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
> + (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
> + (inst (i1 0), $ptr, (as_i16imm $offset))
> +>;
>
> -multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
> - def : Pat <
> - (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
> - (inst (i1 0), $ptr, $value, (as_i16imm $offset))
> - >;
> +def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
> +def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
> +def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
> +def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
> +def : DSReadPat <DS_READ_B32, i32, local_load>;
> +def : DSReadPat <DS_READ_B64, v2i32, local_load>;
>
> - def : Pat <
> - (frag vt:$val, i32:$ptr),
> - (inst 0, $ptr, $val, 0)
> - >;
> -}
> +class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
> + (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
> + (inst (i1 0), $ptr, $value, (as_i16imm $offset))
> +>;
>
> -defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
> -defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
> -defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
> -defm : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
> +def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
> +def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
> +def : DSWritePat <DS_WRITE_B32, i32, local_store>;
> +def : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
>
> multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
> def : Pat <
> diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll
> index 7dec426..e13d719 100644
> --- a/test/CodeGen/R600/32-bit-local-address-space.ll
> +++ b/test/CodeGen/R600/32-bit-local-address-space.ll
> @@ -1,4 +1,5 @@
> -; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
> +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
> +; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=CI --check-prefix=FUNC %s
>
> ; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
> ; the global address space(1) uses 64-bit pointers. These tests check to make sure
> @@ -9,7 +10,7 @@
> ; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
> ; instructions with B64, U64, and I64 take 64-bit operands.
>
> -; CHECK-LABEL: @local_address_load
> +; FUNC-LABEL: @local_address_load
> ; CHECK: V_MOV_B32_e{{32|64}} [[PTR:v[0-9]]]
> ; CHECK: DS_READ_B32 v{{[0-9]+}}, [[PTR]]
> define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
> @@ -19,7 +20,7 @@ entry:
> ret void
> }
>
> -; CHECK-LABEL: @local_address_gep
> +; FUNC-LABEL: @local_address_gep
> ; CHECK: S_ADD_I32 [[SPTR:s[0-9]]]
> ; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
> ; CHECK: DS_READ_B32 [[VPTR]]
> @@ -31,7 +32,7 @@ entry:
> ret void
> }
>
> -; CHECK-LABEL: @local_address_gep_const_offset
> +; FUNC-LABEL: @local_address_gep_const_offset
> ; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
> ; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VPTR]], 0x4,
> define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
> @@ -43,7 +44,7 @@ entry:
> }
>
> ; Offset too large, can't fold into 16-bit immediate offset.
> -; CHECK-LABEL: @local_address_gep_large_const_offset
> +; FUNC-LABEL: @local_address_gep_large_const_offset
> ; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
> ; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
> ; CHECK: DS_READ_B32 [[VPTR]]
> @@ -55,7 +56,7 @@ entry:
> ret void
> }
>
> -; CHECK-LABEL: @null_32bit_lds_ptr:
> +; FUNC-LABEL: @null_32bit_lds_ptr:
> ; CHECK: V_CMP_NE_I32
> ; CHECK-NOT: V_CMP_NE_I32
> ; CHECK: V_CNDMASK_B32
> @@ -66,7 +67,7 @@ define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds)
> ret void
> }
>
> -; CHECK-LABEL: @mul_32bit_ptr:
> +; FUNC-LABEL: @mul_32bit_ptr:
> ; CHECK: V_MUL_LO_I32
> ; CHECK-NEXT: V_ADD_I32_e32
> ; CHECK-NEXT: DS_READ_B32
> @@ -79,7 +80,7 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %
>
> @g_lds = addrspace(3) global float zeroinitializer, align 4
>
> -; CHECK-LABEL: @infer_ptr_alignment_global_offset:
> +; FUNC-LABEL: @infer_ptr_alignment_global_offset:
> ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0
> ; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]]
> define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
> @@ -92,21 +93,21 @@ define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %ti
> @ptr = addrspace(3) global i32 addrspace(3)* null
> @dst = addrspace(3) global [16384 x i32] zeroinitializer
>
> -; CHECK-LABEL: @global_ptr:
> +; FUNC-LABEL: @global_ptr:
> ; CHECK: DS_WRITE_B32
> define void @global_ptr() nounwind {
> store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
> ret void
> }
>
> -; CHECK-LABEL: @local_address_store
> +; FUNC-LABEL: @local_address_store
> ; CHECK: DS_WRITE_B32
> define void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
> store i32 %val, i32 addrspace(3)* %out
> ret void
> }
>
> -; CHECK-LABEL: @local_address_gep_store
> +; FUNC-LABEL: @local_address_gep_store
> ; CHECK: S_ADD_I32 [[SADDR:s[0-9]+]],
> ; CHECK: V_MOV_B32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
> ; CHECK: DS_WRITE_B32 [[ADDR]], v{{[0-9]+}},
> @@ -116,7 +117,7 @@ define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32
> ret void
> }
>
> -; CHECK-LABEL: @local_address_gep_const_offset_store
> +; FUNC-LABEL: @local_address_gep_const_offset_store
> ; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
> ; CHECK: V_MOV_B32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
> ; CHECK: DS_WRITE_B32 [[VPTR]], [[VAL]], 0x4
> @@ -127,7 +128,7 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v
> }
>
> ; Offset too large, can't fold into 16-bit immediate offset.
> -; CHECK-LABEL: @local_address_gep_large_const_offset_store
> +; FUNC-LABEL: @local_address_gep_large_const_offset_store
> ; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
> ; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
> ; CHECK: DS_WRITE_B32 [[VPTR]], v{{[0-9]+}}, 0
> diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll
> index ab2c0bf..cd698f4 100644
> --- a/test/CodeGen/R600/gep-address-space.ll
> +++ b/test/CodeGen/R600/gep-address-space.ll
> @@ -1,4 +1,5 @@
> -; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
> +; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
>
> define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
> ; CHECK-LABEL: @use_gep_address_space:
> @@ -11,7 +12,10 @@ define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
>
> define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %array) nounwind {
> ; CHECK-LABEL: @use_gep_address_space_large_offset:
> -; CHECK: S_ADD_I32
> +; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
> +; SI, which is why it is being OR'd with the base pointer.
> +; SI: S_OR_B32
> +; CI: S_ADD_I32
> ; CHECK: DS_WRITE_B32
> %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
> store i32 99, i32 addrspace(3)* %p
> diff --git a/test/CodeGen/R600/local-64.ll b/test/CodeGen/R600/local-64.ll
> index c52b41b..ef48eef 100644
> --- a/test/CodeGen/R600/local-64.ll
> +++ b/test/CodeGen/R600/local-64.ll
> @@ -1,8 +1,9 @@
> -; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s
> +; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
>
> -; SI-LABEL: @local_i32_load
> -; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
> -; SI: BUFFER_STORE_DWORD [[REG]],
> +; BOTH-LABEL: @local_i32_load
> +; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
> +; BOTH: BUFFER_STORE_DWORD [[REG]],
> define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
> %gep = getelementptr i32 addrspace(3)* %in, i32 7
> %val = load i32 addrspace(3)* %gep, align 4
> @@ -10,19 +11,19 @@ define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounw
> ret void
> }
>
> -; SI-LABEL: @local_i32_load_0_offset
> -; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
> -; SI: BUFFER_STORE_DWORD [[REG]],
> +; BOTH-LABEL: @local_i32_load_0_offset
> +; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
> +; BOTH: BUFFER_STORE_DWORD [[REG]],
> define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
> %val = load i32 addrspace(3)* %in, align 4
> store i32 %val, i32 addrspace(1)* %out, align 4
> ret void
> }
>
> -; SI-LABEL: @local_i8_load_i16_max_offset
> -; SI-NOT: ADD
> -; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
> -; SI: BUFFER_STORE_BYTE [[REG]],
> +; BOTH-LABEL: @local_i8_load_i16_max_offset
> +; BOTH-NOT: ADD
> +; BOTH: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
> +; BOTH: BUFFER_STORE_BYTE [[REG]],
> define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
> %gep = getelementptr i8 addrspace(3)* %in, i32 65535
> %val = load i8 addrspace(3)* %gep, align 4
> @@ -30,11 +31,14 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
> ret void
> }
>
> -; SI-LABEL: @local_i8_load_over_i16_max_offset
> -; SI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
> -; SI: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
> -; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
> -; SI: BUFFER_STORE_BYTE [[REG]],
> +; BOTH-LABEL: @local_i8_load_over_i16_max_offset
> +; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
> +; SI, which is why it is being OR'd with the base pointer.
> +; SI: S_OR_B32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
> +; CI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
> +; BOTH: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
> +; BOTH: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
> +; BOTH: BUFFER_STORE_BYTE [[REG]],
> define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
> %gep = getelementptr i8 addrspace(3)* %in, i32 65536
> %val = load i8 addrspace(3)* %gep, align 4
> @@ -42,10 +46,10 @@ define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspa
> ret void
> }
>
> -; SI-LABEL: @local_i64_load
> -; SI-NOT: ADD
> -; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
> -; SI: BUFFER_STORE_DWORDX2 [[REG]],
> +; BOTH-LABEL: @local_i64_load
> +; BOTH-NOT: ADD
> +; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
> +; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
> define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
> %gep = getelementptr i64 addrspace(3)* %in, i32 7
> %val = load i64 addrspace(3)* %gep, align 8
> @@ -53,19 +57,19 @@ define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounw
> ret void
> }
>
> -; SI-LABEL: @local_i64_load_0_offset
> -; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
> -; SI: BUFFER_STORE_DWORDX2 [[REG]],
> +; BOTH-LABEL: @local_i64_load_0_offset
> +; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
> +; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
> define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
> %val = load i64 addrspace(3)* %in, align 8
> store i64 %val, i64 addrspace(1)* %out, align 8
> ret void
> }
>
> -; SI-LABEL: @local_f64_load
> -; SI-NOT: ADD
> -; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
> -; SI: BUFFER_STORE_DWORDX2 [[REG]],
> +; BOTH-LABEL: @local_f64_load
> +; BOTH-NOT: ADD
> +; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
> +; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
> define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
> %gep = getelementptr double addrspace(3)* %in, i32 7
> %val = load double addrspace(3)* %gep, align 8
> @@ -73,85 +77,85 @@ define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in)
> ret void
> }
>
> -; SI-LABEL: @local_f64_load_0_offset
> -; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
> -; SI: BUFFER_STORE_DWORDX2 [[REG]],
> +; BOTH-LABEL: @local_f64_load_0_offset
> +; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
> +; BOTH: BUFFER_STORE_DWORDX2 [[REG]],
> define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
> %val = load double addrspace(3)* %in, align 8
> store double %val, double addrspace(1)* %out, align 8
> ret void
> }
>
> -; SI-LABEL: @local_i64_store
> -; SI-NOT: ADD
> -; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
> +; BOTH-LABEL: @local_i64_store
> +; BOTH-NOT: ADD
> +; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
> define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
> %gep = getelementptr i64 addrspace(3)* %out, i32 7
> store i64 5678, i64 addrspace(3)* %gep, align 8
> ret void
> }
>
> -; SI-LABEL: @local_i64_store_0_offset
> -; SI-NOT: ADD
> -; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> +; BOTH-LABEL: @local_i64_store_0_offset
> +; BOTH-NOT: ADD
> +; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
> store i64 1234, i64 addrspace(3)* %out, align 8
> ret void
> }
>
> -; SI-LABEL: @local_f64_store
> -; SI-NOT: ADD
> -; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
> +; BOTH-LABEL: @local_f64_store
> +; BOTH-NOT: ADD
> +; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
> define void @local_f64_store(double addrspace(3)* %out) nounwind {
> %gep = getelementptr double addrspace(3)* %out, i32 7
> store double 16.0, double addrspace(3)* %gep, align 8
> ret void
> }
>
> -; SI-LABEL: @local_f64_store_0_offset
> -; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> +; BOTH-LABEL: @local_f64_store_0_offset
> +; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
> store double 20.0, double addrspace(3)* %out, align 8
> ret void
> }
>
> -; SI-LABEL: @local_v2i64_store
> -; SI-NOT: ADD
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
> +; BOTH-LABEL: @local_v2i64_store
> +; BOTH-NOT: ADD
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
> define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
> %gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
> store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
> ret void
> }
>
> -; SI-LABEL: @local_v2i64_store_0_offset
> -; SI-NOT: ADD
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> +; BOTH-LABEL: @local_v2i64_store_0_offset
> +; BOTH-NOT: ADD
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
> store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
> ret void
> }
>
> -; SI-LABEL: @local_v4i64_store
> -; SI-NOT: ADD
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
> +; BOTH-LABEL: @local_v4i64_store
> +; BOTH-NOT: ADD
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
> define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
> %gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
> store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
> ret void
> }
>
> -; SI-LABEL: @local_v4i64_store_0_offset
> -; SI-NOT: ADD
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
> -; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> +; BOTH-LABEL: @local_v4i64_store_0_offset
> +; BOTH-NOT: ADD
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
> +; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
> define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
> store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
> ret void
> diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll
> index e29e4cc..91bee46 100644
> --- a/test/CodeGen/R600/local-memory-two-objects.ll
> +++ b/test/CodeGen/R600/local-memory-two-objects.ll
> @@ -1,5 +1,6 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
> -; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
> +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=SI-ONLY %s
> +; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=CI-ONLY %s
>
> @local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
> @local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
> @@ -28,8 +29,10 @@
> ; constant offsets.
> ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
> ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
> -; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10
> -; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0,
> +; SI-ONLY: V_ADD_I32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
> +; SI-ONLY: DS_READ_B32 {{v[0-9]+}}, [[SIPTR]], 0x0
> +; CI-ONLY: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10
> +; CI-ONLY: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0,
Using a different check prefix naming convention here is weird instead
of SI:, CI:
>
> define void @local_memory_two_objects(i32 addrspace(1)* %out) {
> entry:
> -- 1.8.1.5
>
> 0004-R600-SI-Use-READ2-WRITE2-instructions-for-64-bit-mem.patch
>
>
> From e0a7c56e125701f5f33c49f441c21416edbfa7f1 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 15 Aug 2014 12:02:40 -0400
> Subject: [PATCH 4/4] R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops
> with 32-bit alignment
>
> ---
> lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 27 +++++++++++++++
> lib/Target/R600/AMDGPUInstructions.td | 11 +++++++
> lib/Target/R600/SIInstrInfo.td | 1 +
> lib/Target/R600/SIInstructions.td | 26 +++++++++++++--
> test/CodeGen/R600/unaligned-load-store.ll | 55 +++++++++++++++++++++++++++++--
> 5 files changed, 116 insertions(+), 4 deletions(-)
>
> diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> index 5933919..66daf4e 100644
> --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> @@ -91,6 +91,8 @@ private:
> bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
> unsigned OffsetBits) const;
> bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
> + bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
> + SDValue &Offset1) const;
> void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
> SDValue &SOffset, SDValue &Offset, SDValue &Offen,
> SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
> @@ -785,6 +787,31 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
> return true;
> }
>
> +bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
> + SDValue &Offset0,
> + SDValue &Offset1) const {
> + if (CurDAG->isBaseWithConstantOffset(Addr)) {
> + SDValue N0 = Addr.getOperand(0);
> + SDValue N1 = Addr.getOperand(1);
> + ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
> + unsigned DWordOffset0 = C1->getZExtValue() / 4;
> + unsigned DWordOffset1 = DWordOffset0 + 1;
> + // (add n0, c0)
> + if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
> + Base = N0;
> + Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
> + Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
> + return true;
> + }
> + }
> +
> + // default case
> + Base = Addr;
> + Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
> + Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
> + return true;
> +}
> +
> static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
> return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
> Ptr), 0);
> diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td
> index 0f2b625..cf3bffa 100644
> --- a/lib/Target/R600/AMDGPUInstructions.td
> +++ b/lib/Target/R600/AMDGPUInstructions.td
> @@ -282,6 +282,17 @@ def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
> return isLocalLoad(dyn_cast<LoadSDNode>(N));
> }]>;
>
> +class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
> + return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
> +}]>;
> +
> +def local_load_aligned8bytes : Aligned8Bytes <
> + (ops node:$ptr), (local_load node:$ptr)
> +>;
> +
> +def local_store_aligned8bytes : Aligned8Bytes <
> + (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
> +>;
>
> class local_binary_atomic_op<SDNode atomic_op> :
> PatFrag<(ops node:$ptr, node:$value),
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 5357af9..064a67e 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -192,6 +192,7 @@ def tfe : Operand <i1> {
> //===----------------------------------------------------------------------===//
>
> def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
> +def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
>
> def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
> def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 9181f24..248ff9c 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -2524,7 +2524,18 @@ def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
> def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
> def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
> def : DSReadPat <DS_READ_B32, i32, local_load>;
> -def : DSReadPat <DS_READ_B64, v2i32, local_load>;
> +
> +let AddedComplexity = 100 in {
> +
> +def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
> +
> +} // End AddedComplexity = 100
> +
> +def : Pat <
> + (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
> + i8:$offset1))),
> + (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)
> +>;
>
> class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
> (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
> @@ -2534,7 +2545,18 @@ class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
> def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
> def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
> def : DSWritePat <DS_WRITE_B32, i32, local_store>;
> -def : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
> +
> +let AddedComplexity = 100 in {
> +
> +def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
> +} // End AddedComplexity = 100
> +
> +def : Pat <
> + (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
> + i8:$offset1)),
> + (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
> + (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)
> +>;
>
> multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
> def : Pat <
> diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll
> index 76ea97c..7df7ba0 100644
> --- a/test/CodeGen/R600/unaligned-load-store.ll
> +++ b/test/CodeGen/R600/unaligned-load-store.ll
> @@ -32,9 +32,8 @@ define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> ad
> ret void
> }
>
> -; FIXME: This should use ds_read2_b32
> ; SI-LABEL: @load_lds_i64_align_4
> -; SI: DS_READ_B64
> +; SI: DS_READ2_B32
> ; SI: S_ENDPGM
> define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
> %val = load i64 addrspace(3)* %in, align 4
> @@ -42,9 +41,61 @@ define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspac
> ret void
> }
>
> +; SI-LABEL: @load_lds_i64_align_4_with_offset
> +; SI: DS_READ2_B32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}}, 0x8, 0x9
> +; SI: S_ENDPGM
> +define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
> + %ptr = getelementptr i64 addrspace(3)* %in, i32 4
> + %val = load i64 addrspace(3)* %ptr, align 4
> + store i64 %val, i64 addrspace(1)* %out, align 8
> + ret void
> +}
> +
> +; SI-LABEL: @load_lds_i64_align_4_with_split_offset
> +; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
> +; SI: DS_READ2_B32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}}, 0x0, 0x1
> +; SI: S_ENDPGM
> +define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
> + %ptr = bitcast i64 addrspace(3)* %in to i32 addrspace(3)*
> + %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
> + %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
> + %val = load i64 addrspace(3)* %ptri64, align 4
> + store i64 %val, i64 addrspace(1)* %out, align 8
> + ret void
> +}
> +
> ; FIXME: Need to fix this case.
> ; define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
> ; %val = load i64 addrspace(3)* %in, align 1
> ; store i64 %val, i64 addrspace(1)* %out, align 8
> ; ret void
> ; }
> +
> +; SI-LABEL: @store_lds_i64_align_4
> +; SI: DS_WRITE2_B32
> +; SI: S_ENDPGM
> +define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 {
> + store i64 %val, i64 addrspace(3)* %out, align 4
> + ret void
> +}
> +
> +; SI-LABEL: @store_lds_i64_align_4_with_offset
> +; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x9, 0x9
> +; SI: S_ENDPGM
> +define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 {
> + %ptr = getelementptr i64 addrspace(3)* %out, i32 4
> + store i64 0, i64 addrspace(3)* %ptr, align 4
> + ret void
> +}
> +
> +; SI-LABEL: @store_lds_i64_align_4_with_split_offset
> +; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
> +; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x0, 0x1
> +; SI: S_ENDPGM
> +define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 {
> + %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)*
> + %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
> + %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
> + store i64 0, i64 addrspace(3)* %out, align 4
> + ret void
> +}
> -- 1.8.1.5
>
LGTM
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